3.8 Transistor loads for inverters

There are other kinds of MOSFET's besides the one we have studied so far. Strictly speaking, what we have seen up to nowis called an n-channel enhancement mode MOSFET . It turns out that you can build a MOSFET which looks just like a previous figure , except that by putting some additional impurities under the gateregion, we can arrange it so that there is a channel formed, even with $V_g=0$ . The transistor now has a negative $V_T$ . The process by which the additional impurities are added is called a $V_T$ adjust .

A MOSFET with a negative $V_T$ can be expected to have $I_d-V_{\mathrm{ds}}$ curves similar to those for a positive $V_T$ device, except for one thing. For $V_{\mathrm{gs}}=0$ , the device is already turned on, and so we get a usual MOSFET-type curve. Positive gate voltage turns it on even more, while negative $V_{\mathrm{gs}}$ tends to reduce the drain current. It takes a negative gate voltage to turn the thing off. shows comparative characteristic curves for an enhancement and depletion modedevices.

For an enhancement mode transistor, you have to get $V_g> V_T$ (-1 Volt in this example) to enhance the conductivity or channel to make it conduct. For a depletion mode device, a gate voltage Vgs of0, still finds the device conducting. You have to put some negative voltage on the gate to deplete the channel, in order to turn it off. We now have a depletion mode n-channel MOSFET .

How would we use a depletion mode device in an inverter gate? The answer is fairly straight-forward. In the schematic in , we indicate a depletion mode MOSFET by adding a second line, under the gate, to suggest that a channel alreadyexists in the device, even with no $V_g$ . Note that the gate of the depletion mode transistor (also sometimes called the pull up transistor) is connected to its source, so, in fact, $V_{\mathrm{gs}}$ does equal 0 for this device. The input transistor (or the pull down transistor) is just an enhancement mode MOSFET like we had before. It is nothard to choose appropriate $W$ and $L$ so that $I_{\mathrm{dsat}}$ for the pull up transistor is on the order of the 500A that we need to get our 1 ns rise time on the capacitive load.

In order to get the transfer characteristic for this circuit, we first note that

Well, we solved one problem. At least we have a pull up structure that we can manufacture. It turns out not to be too hard tobuild an enhancement MOSFET that has an equivalent resistance in the range we need without taking up too much chip area. We have notsolved the other problem however. We are still looking at a huge current draw for large circuits. Since on average, half of the inverter gates will be "on" in alogic circuit, we still have a large current sink to ground. This is something that would be completely prohibitive in a modern-day VLSIintegrated circuit.

Fortunately, we have not run out of options for MOS structures yet.