3.9 Cmos logic

Consider the following, shown in .

This looks a lot like our previous MOSFET except that now we have an n-type substrate and the source and drain regions arep-type. If we apply a negative $V_{\mathrm{gs}}$ (with the source connected to the n-type substrate) then the induced negative charge on the gatewill drive away the electrons, and if the bands under the gate are bent up sufficiently, form an inversion layer of holes thus making an enhancement mode p-channel MOSFET , or a PMOS transistor. (As opposed to an NMOS transistor which we studied first.). Notethat a PMOS transistor will have a negative $V_T$ . That is, the gate voltage has to be less than the source/substrate voltage in order to turn the device on. The more negative $V_{\mathrm{gs}}$ , the more current we will have flowing through the device.

It turns out that a combination of both an n-channel and a p-channel device on the same circuit can be veryadvantageous. Such technology is called CMOS , for "complementary MOS". Here is how we use a p-channeltransistor in the inverter circuit.

First of all, however, we have to see how we would make one. There is a fundamental problem in trying to use bothn-channel and p-channel devices in the same circuit. What is it? It would seem we need two different kinds of substrates, both ap-type substrate for the n-channel transistor, and an n-type substrate for the p-channel device. There is a way around thisproblem by making what is called a tank or a moat . A moat is a relatively deep region of one type of material placed into a host substrate of the oppositetype ( ). We can put n-type source/drain regions into the p-substrate and p-type source/drain regionsinto the n-moat. In , we will also show the gates, and how the whole inverter is connected together.

Now let's draw the schematic : A p-channel device is drawn just like an n-channel device, exceptwe put a little "bubble" on the gate to signify that it is a MOSFET of a different color. Although we usually don't do thisall the time, we have also shown the substrate connections in this diagram. These connections show that a MOSFET is at least afour terminal device, not a three terminal one as people often assume. Since, in a p-channel device, the substrate is n-type,we show the substrate connection as an outward pointing arrow. The p-type substrate for the n-channel device is shown asan inward pointing arrow. The n-channel substrate is connected to ground, the p-channel substrate is connected to $V_{\mathrm{dd}}$ . Note that since the n-moat is at $V_{\mathrm{dd}}$ and the p-substrate is at ground, the moat-substrate p-n junction is reverse biased, and so no currentshould flow between them.

We usually do not label the source and drain either, but we do here, just for completeness. Note that unlike the bipolartransistor, the FET is truly a symmetric device. There is really no way to tell the source from the drain. By convention, we callthe element which is connected to the substrate (or moat) the source, and the other the drain. You will sometimes hear theregion under the gate (either substrate or moat) referred to as the backbody .

Now let's see how this circuit works. If $V_{\mathrm{in}}$ is high (at or near $V_{\mathrm{dd}}$ ) the NMOS transistor will be turned on. The voltage between the gate and substrate of the p-channeldevice is at or near zero. The gate is at $V_{\mathrm{dd}}$ and so is the moat! Hence the upper transistor will be turned off. The output will thus be low .

If the input voltage is at or near ground (a "low") then the n-channel device is turned off. The voltage between the gate andsubstrate of the p-channel device is now $\eqsim (-V_{\mathrm{dd}})$ . (The gate is $\eqsim (0)$ and the substrate is at $V_{\mathrm{dd}}$ .) If the PMOS transistor has a threshold voltage $V_T$ of, say, -2 V, then it will be turned on and the output will be high . Note however, that in either state, high or low, there is no static current flowing through the inverter .

The transfer characteristics for this circuit. Are a little more complicated. First, let's make sure we have our voltages andcurrents defined . From the figure, $V_{\mathrm{gs}-n}$ the n-channel gate-source voltage is just Vin. $V_{\mathrm{gs}-p}$ the gate-source voltage for the p-channel device is $V_{\mathrm{in}}-V_{\mathrm{dd}}{I}_{d-n}=I_{d-p}=I_d{V}_{\mathrm{ds}-p}$ the drain source voltage for the p-channel transistor can be written as $V_{\mathrm{ds}-n}-V_{\mathrm{dd}}$ . We have two sets of characteristic curves : Note that since $V_{\mathrm{gs}-p}=V_{\mathrm{in}}-V_{\mathrm{dd}}$ , when $V_{\mathrm{in}}=0$ V, $V_{\mathrm{gs}-p}=-5$ V and so the transistor is strongly turned on.

We have a number of different "load lines" in this case, because for each $V_{\mathrm{in}}$ we have a different curve for both the n and p channel transistors. This is shown in . The black spots show the point of intersection. Follow a few of the curves along to see if youagree with where the spots have been placed. We have also added a pair of dotted curves for $V_{\mathrm{in}}=2.5$ V so we can get the "turn-over" point. Projecting the location of the black dots to the $V_{\mathrm{ds}-n}$ (or $V_{\mathrm{out}}$ ) axis will gives us a value for $V_{\mathrm{out}}$ for each of the input voltages, $V_{\mathrm{in}}$ . The resulting curve is shown in . This gives us a good "feel" for how the inverter works, and how the output varies with the input. Notethat this transfer curve is quite symmetric about 2.5 volts, and goes all the way from +5 to 0 volts on the output.