C6x assembly programming  (Page 7/11)

In many cases, depending on the result of previous operations, you execute the branch instructionconditionally. For example, to implement a loop, you decrement the loop counter by 1 each time you run a set ofinstructions and whenever the loop counter is not zero, you need to branch to the beginning of the code block to iteratethe loop operations. In the C6x CPU, this conditional branching is implemented using the conditional operations . Although B may be the instruction implemented using conditional operationsmost often, all instructions in C6x can be conditional.

Conditional instructions are represented in code by using square brackets, [ ] , surrounding the condition register name. For example, the following B instruction is executed only if B0 is nonzero:

To execute an instruction conditionally when the condition register is zero, we use ! in front of the register. Forexample, the B instruction is executed when B0 is zero.

Not all registers can be used as the condition registers. In the C62x and C67x devices, the registers that can be tested in conditionaloperations are B0 , B1 , B2 , A1 , A2 .

Logical operations and bit manipulation

The logical operations and bit manipulations are accomplished by the AND , OR , XOR , CLR , SET , SHL , and SHR instructions.

Other assembly instructions

Other useful instructions include IDLE and compare instructions such as CMPEQ etc.

C62x instruction set summary

The set of instructions that can be performed in each functional unit is as follows (See [link] , [link] , [link] and [link] ). Please refer to TMS320C62x/C67x CPU and Instruction Set Reference Guide for detailed description of each instruction.