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In a similar fashion IC Technology has been a great leveler of human societies. All human beings are becoming a knowledge worker in one way or the other and the whole world is being rapidly transformed into a big Global Village where all new ideas or new technologies are available to one and all in the shortest time.
Moore’s Law prediction of increase in packing density from generation to generation with scaled down dimensions has enabled the integration of scaled up systems with greater functionalities and integration of bigger memory capacities in the same chip area.
Table 2..1.3.1. Clasification according to the scale of integration.
| SSI | MSI | LSI | VLSI | ULSI |
|---|---|---|---|---|
| <30comp.RTL | 30 to 100comp.Mag.Comp.Chip | 100,000comp4004μP | >1million comp.PentiumIV | >100million comp.Corei7 |
Table 2.1.3.2. MOS Dimension Scaling.
| MOS | 1967 | 1997 | 1999 | 2001 | 2003 | 2006 | 2013 |
|---|---|---|---|---|---|---|---|
| L(μm) | 10 | 0.25 | 0.18 | 0.13 | 0.10 | 0.07 | 32 |
| DRAM(Gb/cm 2 ) | 64M | 0.18 | 0.38 | 0.42 | 0.91 | 1.85 | 32 |
| Junction Depth(x j )nm | 1000 | 100 | 70 | 60 | 52 | 40 | ? |
| Interconnection Pitch(nm) | 2000 | 600 | 500 | 350 | 245 | 70 | 32 |
| Technology | micron | Sub-micron technology | Deep sub-micron | Ultra-Deep-Sub-micron |
Table 2.1.3.3.Processor scaling from 2006 to 2012.
| Processor | MOS count | Year | Manf. | Process | Area(mm 2 ) |
|---|---|---|---|---|---|
| AMD K10 quad core2ML3 | 463M | 2007 | AMD | 65nm | 283 |
| AMD K10 quad core6ML3 | 758M | 2008 | AMD | 45nm | 258 |
| Corei7(quad) | 731M | 2008 | Intel | 45nm | 263 |
| 6Core Opteron 2400 | 904M | 2009 | AMD | 45nm | 346 |
| 16Core Sparc T3 | 1B | 2010 | SUN/ORACLE | 40nm | 377 |
| 6Core Corei7 | 1.17B | 2011 | INTEL | 32nm | 216 |
| QuadCore+GPU Corei7 | 1.4B | 2012 | INTEL | 22nm | 160 |
| 62Core Xeon Phi | 5B | 2012 | INTEL | 22nm | ? |
Table 2.1.3.4.GPU scaling from 1997 to 2012. [GPU – Graphical Processing Unit is a specialized electronic circuit designed to rapidly manipulate and alter memory to accelerate the building of images in a frame buffer intended for output to display]
| Processor | MOS count | Year | Manf. | Process | Area(mm 2 ) |
|---|---|---|---|---|---|
| NV3 | 3.5M | 1997 | NVIDIA | 350nm | 90 |
| Tahiti RV1070 | 4.3B | 2011 | AMD | 28nm | 365 |
| GK110Kepler | 7.08 | 2012 | NVIDIA | 28nm | 561 |
Table 2.1.3.5.FPGA (Field Programmable Gate Array). It can be configured by the user according to his sysyem requirements. With increase in components the options for configurability is getting enhanced day by day.
| FPGA | MOS count | Year | Manufacturer | Process |
|---|---|---|---|---|
| VIRTEX | 70M | 1997 | Xilinx | ? |
| VITEX II | 350M | 2000 | Xilinx | 130nm |
| Virtex 4 | 1B | 2004 | Xilinx | 90nm |
| Stratia IV | 2.5B | 2008 | Altera | 40nm |
| Virtex 7 | 6.8B | 2011 | Xilinx | 28nm |
We have already seen in Section 2.1.2.6. that CMOS, because of its nanowatt power dissipation in stand-by mode, is becoming the technology of choice at the lecvel of ULSI. All applications are converging to CMOS process technology.
Theoretical proposition of CMOS as nano-watt logic family was made in1963 at International Solid-State-Circuits Conference(ISSCC-1963).
In 1968, RCA commercialized CMOS series of logic family known as CD4000 series. This was equivalent to TTL 74series.
Till 1970 the Industry Consensus was:
1.Mainstream device will remain NMOS.
2.BJT will be for Analog applications and for very high speed applications.
3.PMOS will be phased out.
4.CMOS will remain the process technology for Wrist Watches ICs.
This consensus was driven by the economic criteria. CMOS technology had a high cost factor. But in 1978, Hitachi pioneered a more economic way of fabricating CMOS products based on the invention of twin well CMOS by Y.Sakai and T.Masuchari then at Hitachi Center for Research Lab. In 1978, Hitachi marketed 4kSRAM based onCMOS which outperformed Intel’s equivalent 4kSRAM based on NMOS technology.
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