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10.1 Measuring key transport properties of fet devices  (Page 4/4)

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Measurement analysis

Typical v-i characteristics of jfets

Voltage sweeps are a great way to learn about the device. [link] shows a typical plot of drain-source voltage sweeps at various gate-source voltages while measuring the drain current, I D for a n-channel JFET. The V-I characteristics have four distinct regions. Analysis of these regions can provides critical information about the device characteristics such as the pinch off voltage, V P , transcunductance gain, g m , drain-source channel resistance, R DS , and power dissipation, P D .

A plot of the drain-source voltage sweeps at various gate voltages with the corresponding drain current measurements of an "ideal" n-channel JFET. The four characteristic regions, Ohmic, saturation, breakdown, and pinch-off, are labeled. Figure adapted from Electronic Tutorials (http://www.electronic-tutorials.ws).

Ohmic region (linear region)

This region is bounded by V DS <V P . Here the JFET begins to flow a drain current with a linear response to the voltage, behaving like a variable resistor. In this region the drain-source channel resistance, R DS is modeled by [link] , where ΔV DS is the change in drain-source voltage, ΔI D is the change in drain current, and g m is the transcunductance gain. Solving for g m results in [link] .

R DS = ΔV DS ΔI D = 1 g m size 12{R rSub { size 8{ ital "DS"} } = { {ΔV rSub { size 8{ ital "DS"} } } over {ΔI rSub { size 8{D} } } } = { {1} over {g rSub { size 8{m} } } } } {}
g m = ΔI D ΔV DS = 1 R DS size 12{g rSub { size 8{m} } = { {ΔI rSub { size 8{D} } } over {ΔV rSub { size 8{ ital "DS"} } } } = { {1} over {R rSub { size 8{ ital "DS"} } } } } {}

Saturation region

This is the region where the JFET is completely “ON”. The maximum amount of current is flowing for the given gate-source voltage. In this region the drain current can be modeled by the [link] , where I D is the drain current, I DSS is the maximum current, V GS is the gate-source voltage, and V P is the pinch off voltage. Solving for the pinch off voltage results in [link] .

I D = I DSS 1 − V GS V P 2 size 12{I rSub { size 8{D} } =I rSub { size 8{ ital "DSS"} } left (1 - { {V rSub { size 8{ ital "GS"} } } over {V rSub { size 8{P} } } } right ) rSup { size 8{2} } } {}
V P = 1 − V GS I D I DSS size 12{V rSub { size 8{P} } =1 - { {V rSub { size 8{ ital "GS"} } } over { sqrt { { {I rSub { size 8{D} } } over {I rSub { size 8{ ital "DSS"} } } } } } } } {}

Breakdown region

This region is characterized by the sudden increase in current. The drain-source voltage supplied exceeds the resistive limit of the semiconducting channel, resulting in the transistor to break down and flow an uncontrolled current.

Pinch-off region (cutoff region)

In this region the gate-source voltage is sufficient to restrict the flow through the channel, in effect cutting off the drain current. The power dissipation, P D , can be solved utilizing Ohms law (I = V/R) for any region using [link] .

LEED IV curve

The p-channel JFET V-I characteristics behave similarly except that the voltages are reversed. Specifically, the pinch off point is reached when the gate-source voltage is increased in a positive direction, and the saturation region is met when the drain-source voltage is increased in the negative direction.

Typical v-i characteristics of mosfets

[link] shows a typical plot of drain-source voltage sweeps at various gate-source voltages while measuring the drain current, I D for an ideal n-channel enhancement MOSFET. Like JFETs, the V-I characteristics of MOSFETS have distinct regions that provide valuable information about device transport properties.

A plot of the drain-source voltage sweeps at various gate voltages with the corresponding drain current measurements of an "ideal" n-channel enahnced MOSFET. Here +ve means that the gate-source voltage is increased in the positive direction. Figure adapted from Electronic Tutorials (http://www.electronic-tutorials.ws).

Ohmic region (linear region)

The n-channel enhanced MOSFET behaves linearly, acting like a variable resistor, when the gate-source voltage is greater than the threshold voltage and the drain-source voltage is greater than the gate-source voltage. In this region the drain current can be modeled by [link] , where I D is the drain current, V GS is the gate-source voltage, V T is the threshold voltage, V DS is the drain-source voltage, and k is the geometric factor described by [link] , where µ n is the charge-carrier effective mobility, C OX is the gate oxide capacitance, W is the channel width, and L is the channel length.

FET2
k = μ n C OX W L size 12{k=μ rSub { size 8{n} } C rSub { size 8{ ital "OX"} } { {W} over {L} } } {}

Saturation region

In this region the MOSFET is considered fully “ON”. The drain current for the saturation region is modeled by [link] . The drain current is mainly influenced by the gate-source voltage, while the drain-source voltage has no effect.

I D = k V GS − V T 2 size 12{I rSub { size 8{D} } =k left (V rSub { size 8{ ital "GS"} } - V rSub { size 8{T} } right ) rSup { size 8{2} } } {}

Solving for the threshold voltage V T results in [link] .

V T = V GS − I D k size 12{V rSub { size 8{T} } =V rSub { size 8{ ital "GS"} } - sqrt { { {I rSub { size 8{D} } } over {k} } } } {}

Pinch-off region (cutoff region)

When the gate-source voltage, V GS , is below the threshold voltage V T the charge carriers in the channel are not available “cutting off” the charge flow. Power dissipation for MOSFETs can also be solved using equation 6 in any region as in the JFET case.

Fet v-i summary

The typical I-V characteristics for the whole family of FETs seen in [link] are plotted in [link] .

Plot of V-I characteristics for the various FET types. Adapted from P. Horowitz and W. Hill, in Art of Electronics, Cambridge University Press, New York, 2 nd Edn., 1994.

From [link] we can see how the doping schemes that lead to enhancement and depletion are displaced along the V GS axis. In addition, from the plot the ON or OFF state can be determined for a given gate-source voltage, where (+) is positive, (0) is zero, and (-) is negative, as seen in [link] .

The ON/OFF state for the various FETs at a given gate-source voltages where (-) is a negative voltage and (+) is a positive voltage.
FET Type V GS = (-) V GS = 0 V GS = (+)
n-channel JFET OFF ON ON
p-channel JFET ON ON OFF
n-channel depletion MOSFET OFF ON ON
p-channel depletion MOSFET ON ON OFF
n-channel enhancement MOSFET OFF OFF ON
p-channel enhancement MOSFET ON ON OFF

Bibliography

  • US Patent, US2524035A, 1950.
  • P. Horowitz and W. Hill, in Art of Electronics, Cambridge University Press, New York, 2 nd Edn., 1994.
  • Electronics Tutorials, http://www.electronics-tutorials.ws/ (accessed February 2015).
  • C. Alexander and M. Sadiku, in Fundamentals of Electric Circuits , McGraw-Hill Education, New York, 4 th Edn., 2009.
  • Interactive Explanations for Semiconductor Devices, http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/index.html (accessed February 2015).
  • D. Neamen, in An Introduction to Semiconductor Devices , McGraw-Hill Education, New York, 1 st Edn., 2005.
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Source:  OpenStax, Physical methods in chemistry and nano science. OpenStax CNX. May 05, 2015 Download for free at http://legacy.cnx.org/content/col10699/1.21
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