Fixed point arithmetic  (Page 2/4)

For example, we interpret an 8-bit binary word $$b_7{b}_6{b}_5{b}_4{b}_3{b}_2{b}_1{b}_0$$ as an integer $$x=-(b_{7}2^7)+b_{6}2^6++b_1\times 2+b_0=-(b_{7}2^7)+\sum_{i=0}^6 2^i{b}_i$$ in the 2's complement representation, and $x$ ranges from $-128$ ( $-2^7$ ) to $127$ ( $2^7-1$ ). Several examples:

When $x$ is a positive (negative) number in 2's complement format, $-x$ can be found by inverting each bit and adding $1$ . For example, $01000000$ is $64$ in decimal and $-64$ is found by first inverting the bits to obtain $10111111$ and adding $1$ , thus $-64$ is $11000000$ as shown in the above table. Because the MSB indicates the sign of the numberrepresented by the binary word, we call this bit the sign bit . If the sign bit is 0, the word represents positive number, while negative numbers have 1as the sign bit.

In 2's compliment representation, subtraction of two integers can be accomplished by usual binary summation bycomputing $x-y$ as $x+-y$ . We investigate the operations on the 2's compliment numbers later . However, when you add two 2's complement numbers, you must keep in mind that the 1 inMSB is actually -1.

Sometimes, you need to convert an 8-bit 2's complement number to a 16-bit number. What is the 16-bit 2's complementnumber representing the same value as the 8-bit numbers $01001011$ and $10010111$ ? The answer is $0000000001001000$ and $1111111110010111$ . For nonnegative numbers (sign bit = 0), you simply addenough 0's to extend the number of bits. For negative numbers, you add enough 1's. This operation is called sign extension . The same rule holds for extending a 16-bit 2's complement number to a 32-bit number.

For the arithmetic assembly instructions, C62x CPU has different versions depending on how it handles the signs.For example, the load instructions LDH and LDB load halfword and byte value to a 32-bit register with sign extension. That is, the loadedvalues are converted to 32-bit 2's complement number and loaded into a register. The instructions LDHU and LDBU do not perform sign extension. They simply fill zeros for theupper 16- and 24-bits, respectively.

For the shift right instructions SHR and SHRU , the same rule applies. The ADDU instruction simply treats the operands as unsigned values.

Fractional representation

Although using 2's compliment integers we can implement both addition and subtraction by usual binary addition (withspecial care for the sign bit), the integers are not convenient to handle to implement DSP algorithms. Forexample, If we multiply two 8-bit words together, we need 16 bits to store the result. The number of required wordlength increases without bound as we multiply numbers together more. Although not impossible, it is complicatedto handle this increase in word-length using integer arithmetic. The problem can be easily handled by usingnumbers between $-1$ and $1$ , instead of integers, because the product of two numbers in $\left[-1 , 1\right]$ are always in the same range.