9.5 Sspd_chapter 7_part 3_electrical properties of moscontinued3  (Page 2/2)

(D)NMOS is transistor 2 which acts as the load to the driver transistor 1. Load (D)NMOS has its Gate shorted to Source hence V _GS = 0V curve applies to the load I-V characteristics which is shown in the lower graph in isolation. It is a non-linear resistance accordingly the load line produced on the output plane of driver transistor (E)NMOS is also non-linear as shown in Figure 7.3.10.4. The slope of the load line is primarily determined by the Triode Region of (D)NMOS.

At low V _ds the above equation reduces to:

Therefore:

W 2 /L 2 = aspect ratio of the active load or transistor 2.

In Figure 7.3.10.4., the non-linear load line is drawn on the output plane of (E)NMOS and the intersection of the load line and the output curve under input high condition and under input low condition gives us the two Q points of the driver transistor as shown in Table 7.3.10.2..

Table 7.3.10.2 The two Q points corresponding to I/P low and I/P high.

The triode portion of the output curve corresponding to V _GS (T1) = +4V determines Z _pd .

From Equation 7.3.14, Z _pd is derived to be:

From Figure 7.3.10.4, we can extract the inverter transfer characteristics. The point of intersections between the load line and output curves corresponding to different values of input voltage = gate voltage give the transfer characteristics of the inverter as tabulated in Table 7.3.10.3 and shown in Figure 7.3.10.5.

Table 7.3.10.3

This transfer characteristics and inversion pont is sensitive to geometrical variations in W and L and to the variation in the ratio of pull-up to pull-down resistances ratio as shown in Figure 7.3.10.6. The point where the locus of Vin = Vout and Transfer Characteristics intersect is called the inversion point(Vinv). We have the best Noise Margin if Vinv = 0.5Vdd.

7.3.10.2. Theoretical formulation of Pull-Up to Pull-down resistances for different configurations.

There can be two configurations of NMOS Inverter. Inverter can be driven by a preceding inverter or it can be driven by a Pass Transitor as shown in Figure 7.3.10.7.

Refer to Figure 7.3.10.2. For best noise margin we choose Vin = Vinv = 0.5Vdd. At this point both the transistors are in Saturation Region(Pentode Region). In Pentode Region the following equation is applicable:

Under steady state condition:

I _DS2 = I _DS1 .

Substituting the appropriate vales in Eq.7.3.16 we get:

Let

Making the proper substitutions we obtain:

Further Simlification yields:

By substituting the typical values of different parameters namely:

V _t = 1V, V _td = -3V, V _inv = 2.5V (for equal noise margin) we get:

7.3.10.2.1. Pull-Up to Pull-down ratio when NMOS Invereter is driven through pass transistors.

The second arrangement in Figure 7.3.10.7 is an NMOS Inverter driven by one or more pass transistors. Here the signal while being transmitted through Pass Transistor will get degraded (Vdd gets reduced to [Vdd-Vtp]) and may give erroneous result. The requirement is that the degradation of the signal by V _tp should not effect correct signal processing This implies that

Inverter 1: Vin=Vdd gives Vout=0.75V and for

Inverter 2:Vin=Vdd-Vtp should also give Vout=0.75V.

Table 7.3.10.4 gives the states of the 4 transistors in the two inverters 1 and 2 when driven by Vdd and [Vdd-Vtp] respectively.

Table 7.3.10.4. The states of the 4 transistors in the two inverters 1 and 2 when driven by Vdd and [Vdd-Vtp] respectively.(Refer to Figure 7.3.10.4)

For Inverter1, in pd(T1):

Since V _ds1 = 0.75V therefore V _ds1 /2 can be neglected and the expression of R ₁ is as follows:

For the load, V _DS2 = 4.25V hence puT(2) is in Pentode region with Vgs = 0V.the transistor current I is:

Here Zpd1 and Zpu1 refer to the transistors in Inverter1. The circuit model for this I/P high is shown in Figure 7.3.10.8. pd(T1) is represented by R1 and pu(T2) is represented by a current source I _DS2 .

But I _DS1 = I _DS2 therefore;

Substituting the values of R ₁ and I _DS2 from above we get:

Consider Inverter 2: when Vin = V DD -V tp .

We do exactly the same calculation as for Inverter1.

Pull-down NMOS is R ₂ .

Pull-up NMOS is Saturated.

Therefore V _out2 of Inverter 2 with V _in = V _DD – V _tp is given as:

If the pass transistor introduces no degradation in operation then in both the inverters we should get the same output even though the second inverter is receiving a degraded Input for High condition.

Therefore

Therefore

Substiturting the defacto values:

V _t = 0.2V _DD =1V and V _tp = 0.3V _DD =1.5V

We get:

Or

Or

We saw that Inverter driven directly by Inverter should have

Inverter driven through a pass transistor should have: