9.26 Sspd_chapter 7_part 7_scaling of mos circuits.  (Page 4/4)

In Table 7.7.5 the effect of Alpha parameter on the cost metrics of Alpha21264C (die

area = 1.15cm ² ) processor is studied.

Table 7.7.5. Total cost of a processor Alpha21264C(die area = 1.15cm 2 ) versus alpha parameter.

Increase in levels of interconnection causes only a slight reduction in yield and hence a slight increase in total cost. This means that improved routability of the signal in the IC Chip is inexpensive.

7.7.5. Wafer size transition from 200mm to 300mm and now to 450mm.

IC Industry’s ability to increased productivity by 25 to 30% per year is the combined result of wafer size transitions, shrinking device geometries, equipment productivity improvement and incremental yield improvements. Wafer size transitions historically account for 4% out of the stated 25-30% productivity increase. This is precisely why wafer size has been increasing periodically as shown in Table 7.7.6.

Table 7.7.6. Wafer size transition leading to increased throughput and increased productivity and decreased unit cost.

WD-Wafer diameter, WC-Wafer cost, D-defect,DA- die area , D/W- gross dies per wafer,FD- functional die.

Starting wafer cost per unit would be reduced by 30% under wafer size increase according to VLSI Research from 1970 onward.

Table 7.7.6 clearly indicates that with increase in Wafer size the scale of economy of IC production improves. With constant die area, yield remains constant but if functionality increase leads to increased die area then defect density will have to be brought down concomitantly so that the product of defect density and die area is constant to ensure constant yield . The constantancy in the die yield only will ensure improved scale of economy.

Driving force for all wafer size transitions include factors of ever increasing die size and increasing number of integrated functions per chip.

Trends indicate that wafer size transitions industry-wide have typically enabled 4% per year productivity improvement and transition to 300mm wafer size should provide 2 to 4% per year lower IC cost per cm ² .

7.7.5.1. Hydrogen injection process to keep the defect density at the lowest with increase in wafer size.

Hydrogen injection during wafer manufacturing has helped in the following manners:

1. Improved uniformity across the wafer, across the run and from run to run;
2. Control of defects such as oxidation induced stacking faults and control of point defects simultaneous process.

Hydrogen injection produces higher yields helping to improve cost effectiveness.

7.7.6. Design options offered by Scaling and Wafer size transition..

Scaling gives us a higher transistor budget meaning higher transistor density. So for same functionality die area can be decreased and for same die area functionality can be increased.

For same die area, increased functionality means more transistors and hence more features. This will pay off in terms of increased CPU performance. This is called addition of performance-enhancing functionality to a processor die.

In the second option where we go for the same functionality and reduced die area we have four dividends:

1. we get a higher yield and hence decreased die cost;
2. reduced power dissipation because of reduced silicon area;.
3. higher clock rate if power dissipation is maintained at original level;
4. Or a combination of higher clock rate and reduced power dissipation.

Wafer size increases and concomitant defect density reduction allows the yield to be maintained constant even with increased die area. Thus number of functional chips per wafer are kept constant though much larger in size and much larger in performance enhancing functionality.

Processor’s power consumption and dissipation has been on the increase along with die size. This is creating the limitation of Fire Wall (P ₀ Watts= power dissipation density×die area) , the maximum limit of dissipation which can be tolerated by a silicon chip.

Here again we have two options:

1. Multi-core procesors which is a combination of smaller , cheaper and less power hungry processor working in parallel to do the same job or
2. Single core processor which is larger, more expemsive and more power hungry.

Manufacturer’s are opting for multi-core processors.

TodayMobile Computing demands that more functionality be added to a single die but not for the purpose of increased performance buit for an ideal mobile computing environment. This will mean combining non-volatile memory, volatile memory, CPU, multiple types of wireless capabilities (blue tooth, 802.11b, 802.11g, GSM e.t.c) on a single die. Here again we can integrate them on ta single die or combine multiple chips with multiple functions into a single module.