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| Chip | Die cost($) | Package | Test&Assembly Cost($) | Total cost($) | ||
| pins | type | Cost($) | ||||
| 386DX | 4 | 132 | QFP | 1 | 4 | 9 |
| 486DX2 | 12 | 168 | PGA | 11 | 12 | 35 |
| PowerPC601 | 53 | 304 | QFP | 3 | 21 | 77 |
| HPPt7100 | 73 | 504 | PGA | 35 | 16 | 124 |
| DECα | 149 | 431 | PGA | 30 | 23 | 202 |
| SuperSPARC | 272 | 293 | PGA | 20 | 34 | 326 |
| Pentium | 417 | 273 | PGA | 19 | 37 | 473 |
As we see that with increasing complexity and increasing number of functions per chip, die area is bound to increase as it has in 5 th column of Table 7.7.1. Increased die area means reduced die yield which will mean increased die cost hence chip cost.
The manufacturing process dictates the wafer cost, wafer yield, and defect density So, the sole control of the designer is the die area – how much functionality should be packed into a chip for it to be “the most cost effective”?
Empirically cost per die grows roughly as the square of the die area. Infact it is a non-linear function of die area.
7.7.4. Cost metrics dependence on Die Area, on Defect Density and on Alpha(circuit manufacturing complexity parameter)
In 2006, for 90nm Generation Devices ‘Alpha 21264C’ fabricated on 300mm Wafer,
the density of defects=0.5per cm 2 and alpha,α,=4.
The cost of 300mm Wafer was $4700 and wafer yield was 95%.
Using Eq.7.7.3, dies/wafer = 231.
Using Eq.7.7.4, die yield = 0.555
Therefore Good dies/wafer= 128.
‘Alpha 21264C’ chip has 524-pin CLGA package.
Using 7.7.1
By a similar algorithm, the total variable costs of 5 Processors are calculated and tabulated in Table.7.7.3.
Table 7.7.3. Variable costs of 5 Processors using 90nmGeneration Technology and 300mm Wafer.(Part I)
| μP | Die area(mm 2 ) | Pin | Wafer cost($) | Package | Dies/Wafer | Die yield |
| Alpha212646C | 115 | 524 | 4700 | CLGA | 231 | 0.555 |
| Power 3-II | 163 | 1088 | 4000 | SLC | 157 | 0.452 |
| Itanium | 300 | 418 | 4910 | PLC | 79 | 0.266 |
| MIPS R14000 | 204 | 527 | 3700 | CPGA | 122 | 0.383 |
| Ultra SPARCIII | 210 | 1368 | 5200 | FC-LGA | 118 | 0.374 |
Table 7.7.3. Variable costs of 5 Processors using 90nmGeneration Technology and 300mm Wafer.(Part II)
| Functional dies/wafer | Die cost($) | Test cost($) | Package Cost($) | Total cost($) |
| 128 | 36.72 | 5.5 | 25 | 67.22 |
| 71 | 56.34 | 5.16 | 20 | 81.50 |
| 20 | 245 | 12.54 | 20 | 277.54 |
| 46 | 80.43 | 7.98 | 25 | 113.41 |
| 44 | 118.18 | 10.7 | 30 | 158.88 |
As we have already noted and it is further verified from Table 7.7.3 that total cost is a nonlinear function of the die area. Generally it is square of the die area.
7.7.4.1. Effect of the Defect density on the cost metrics.
In Table 7.7.4, the effect of defect density on the cost metrics is evaluated.
Table 7.7.4.Total cost of a processor ITANIUM (die area=3cm 2 ) versus defect density with Wafer diameter of 300mm.
| Defect density(d/cm 2 ) | D/W | Y | FD/W | DC($) | TC($) | Package Cost($) | Total cost($) |
| 0.3 | 79 | 0.422 | 33 | 148.8 | 7.9 | 20 | 176.39 |
| 1 | 79 | 0.101 | 8 | 612.58 | 32.91 | 20 | 665.41 |
D/W – dies per wafer, Y- die yield, FD/W – functional dies per wafer, DC- die cost, TC- test cost.
As is evident from Table 7.7.4, increase in defect density has drastic reduction effect on the yield and hence it has drastic enhancement effect on the die cost. So defect density has to be kept under tight control and it needs to be reduced as die area is increased if the die yield has to be maintained at a constant level.
7.7.4.2. Effect of Alpha (manfactruring complexity parameter) on Cost Metrics.
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