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In mid-70s, all the parts of CPU were put on one die for μP 8086 (16-bit processor, 40 pin DIP package) as shown in Figure 7.7.2.
In 80s μP80286 and μP80386 were introduced which had ×87 Floating-point hardware on a separate chip on the same mother board.
In 1989 , tightly pipe-lined 8086 architecture was introduced as μP80486. This included ×87 Floating-point hardware on-die.
In 1990s, Single Instruction Multiple Data (SIMD) started out as a separate chip. SUN Microsystyem moved it on-chip when VIS was introduced to UltraSPARC.
In 1992-93 Pentium was introduced which had CPU+Memory+Input/Output port built on the same chip plus it had a second ALU. It was a Intel’s first superscalar processor.
Figure 7.7.3. Photograph of hermetically sealed Pentium 4 chip with 423 and 478-pin PGA packages.
L1 cache was moved on-die in Pentium 2 Architecture.
Latest Pentium architecture started out with a 400 MHz system bus and 256KB L2 cache (later increased to 800 MHz and 2MB). The first models contained 42 million transistors, used the 0.18 micron process and came in 423-pin and 478-pin PGA packages. Intel's first Pentium 4 chipset was the 850 and supported only Rambus memory (RDRAM), but subsequent chipsets switched to DDR SDRAM.
Subsequently Floating-point hardware moved on-die.
Thus new features were added in scaled down chip to add performance-enhancing functionality to a processor die.
7.7.3. Cost Metrics of IC Chip.
Final Test yield is the % of successful dies produced hence it is unity or less.
The die cost is calculated by the formula:
The denominator of Eq.7.7.2 gives the the total number of good dies or expected number of working dies achieved on a given wafer. It is the product of total number of dies achieved on a wafer and the yield of the given wafer.
Dies per wafer is calculated by the following formula:
Where D = wafer diameter in cm and S = die area in cm 2 .
Rewriting Eq.7.7.3 we get:
Eq.7.7.3a can be interpreted as:
Yield of the dies from a wafer is calculated by the following formula:
Where wafer yield is generally 100% meaning wafer is perfect,
defect/area is given as defects per cm 2 and die area in cm 2 is to be used.
There are 3 kinds of defects: random, systematic and parametric. Here we are concerned with random defects which is a measure of random manufacturing defects on the wafer.
α = empirical parameter that corresponds to the critical masking levels, a measure of manufacturing complexity of the circuit.
Using Eq 7.7.4 and Eq.7.7.3 in conjunction with Eq.7.7.2, the die cost is calculated for seven processor chips as given in Table 7.7.1.
Table 7.7.1.Die Cost of various processors.
| Chip | Wafer dia.(mm) | WaferCost($) | DefectPer cm 2 | Die Area(mm 2 ) | Diesperwafer | Yield(%) | DieCost($) |
| 386DX | 150 | 900 | 1 | 43 | 360 | 71 | 4 |
| 486DX2 | 150 | 1200 | 1 | 81 | 181 | 54 | 12 |
| PowerPC601 | 150 | 1700 | 1.3 | 121 | 115 | 28 | 53 |
| HPPt7100 | 150 | 1300 | 1 | 196 | 66 | 27 | 73 |
| DECα | 150 | 1500 | 1.2 | 234 | 53 | 19 | 149 |
| SuperSPARC | 150 | 1700 | 1.6 | 256 | 48 | 13 | 272 |
| Pentium | 150 | 1500 | 1.5 | 296 | 40 | 9 | 417 |
Using Eq.7.7.1 we calculate the cost of the seven processors as given in Table 7.7.2.
Table 7.7.2. IC Chip variable Costs.
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