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D1,D3,D4 and D6 are sidewall diodes and D2&D5 are the bottom diodes. Table 7.6.2 in the 5 th row accounts for the capacitance associated with D2&D5 only. The side wall diodes junction capacitances are called peripheral capacitances and have not been accounted for.
Similarly N+Source and N+Drain diffusion into P-substrate have created D7,D9,D10 and D12 sidewall diodes and D8&D11 bottom diodes. Here also 5 th Row of Table 7.6.2 acounts for D8&D11 botom diodes only.Peripheral diodes junction capacitance remain to be accounted for.
As we scale downGeneration after Generation the relative value of peripheral capacitances increases with respect to area capacitances(or bottom capacitances).
If instead of diffusion, the active regions are achieved by ion-implantation then because of the very shallow depths of the active regions the sidewall capacitances are insignificant and hence can be neglected.
Table 7.6.9.1 gives the values of the bottom junction capacitances and sidewall junction capacitances.
Table 7.6.9.1.Typical values for diffusion capacitances .
| Typical values of junction capacitances, bottom and sidewall. | |||
| 5μm | 2μm | 1.2μm | |
| Area Capacitance(C area ) | 1.0×10 -4 pF/μm 2 | 1.75×10 -4 pF/μm 2 | 3.75×10 -4 pF/μm 2 |
| Peripheral Capacitance(Cperiph) | 8.0×10 -4 pF/μm 2 | Ion-implant | Ion-implant |
7.6.9.6. Choice of layers according to the suitability of their functions.
Metal Layers , poly-silicon layers, diffusion layers are chosen according to the functions which they are to perform.
Lower is the value of relative permittivity closer is the velocity of propogation to ‘c’(velocity of light in free space)..
Table 7.6.9.2 gives the maximum length of communication lines based on the speed of
switching consideration.
Table 7.6.9.2.Electrical Rules for communication lines.
| layer | Maximum legth of communication wire | ||
| Lambda-based(5μm) | μm-based(2μm) | μm-based(1.2μm) | |
| Metal | Chip wide | Chip wide | Chip wide |
| Silicide | 2000λ | NA | NA |
| Polysilicon | 200λ | 400μm | 250μm |
| Diffusion(active) | 20λ* | 100μm | 60μm |
*Taking into account of peripheral and area capacitances. NA=not applicable.
Table 7.6.9.3 gives the thickness values of different layers in 0.8μm CMOS process.
Table7.6.9.3.Thickness values of different layers(0.8μm CMOS process)
| Layer | Thickness(μm) |
| Field Oxide | 0.52 |
| Gate Oxide | 16nm |
| Poly-Si thickness | 0.35 |
| Poly-Metal Oxide thickness | 0.65 |
| Metal 1 thickness | 0.60 |
| Via Oxide thickness | 1.00 |
| Metal 2 thickness | 1.00 |
| N+ junction depth | 0.40 |
| P+ junction depth | 0.40 |
| N-Well junction depth | 3.5 |
Different terms used in Table 7.6.9.3 are explained in Figure 7.6.9.6.
In Table 7.6.9.4. we give the functional suitability of different layers.
Table 7.6.9.4.Functional suitability of different layers.
| Layer | R | C | Comments |
| Metal | low | low | Use for power distribution and global signals |
| Silicide | low | moderate | Modest RC delay. Reasonably long wires are possible. Silicide is used in place of Poly-Si in some NMOS processes |
| Poly-Si | high | moderate | Moderate RC delay and high IR drop |
| Diffusion(active) | moderate | high | Moderate IR drop but high C hence hard to drive. |
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