9.1 Sspd_chapter 7_part 1_the art of microchip fabrication transforms  (Page 4/4)

Figure 7.8. Levels of abstraction versus Year.

Levels of abstraction tomorrow??

Figure 7.9. Levels of abstraction in Future.

What designers need

is to have abstraction levels removed ,

not added

What designers need… is RTL signoff

Designer thinks about:

System code, RTL code,

System simulation, RTL simulation

Vendor thinks about:

everything else

Levels of abstraction: RTL signoff

Figure 7.10. With RTL signoff, level of abstraction comes down to 4 level. As complexity increases the levels again start adding.

What designers need…

• Physical synthesis

+ Improve quality of synthesis

+ Improve quality of place&route

+ No more gate tweaks and layout modules

+ No longer worry about gate-level timing

• Automatic verification of RTL vs netlist

+ No longer worry about netlist simulation

• RTL analysis tools for timing, power, area

• Smarter IP lawyers

Things to consider

about new EDA tools

• How do they fit into my existing design flow?

• Revolutionary or evolutionary?

• What problems do they solve?

• What new problems might they introduce?

Higher-level abstractions place you further away from

an intuitive feel for hardware and timing: “How fast is it?”

Just because you can do something,

doesn’t mean it is worth doing

• Chip Design.

These are carried out at five levels of abstraction:

1. System level;
2. Logic level;
3. Circuit level;
4. Layout level;
5. Technological level.

Chip Design starts with product specification followed by front end design and back end design.

Front end design starts from system level and goes to the lower level using top-down approach. Up to logic level we are not concerned if we are using Bipolar Technology or MOS technology. After the logic level we come to circuit level. At circuit level, the logic functionality, timing delays, speed and power are the primary concerns. This level is technology dependent it is relatively process-independent.

At the back-end, the final design needs to be translated into the physical layout. This SSPD_chapter 7 is concerned with the physical layout.

At the front-end we have electronic computer-aided design(ECAD). These are so powerful today that the logic design can be synthesized from a high level description language such as VHDL or Verilog. The circuit netlist can be extracted from the logic functional description and the layout can be extracted from the circuit and logic-level. This part is full well explained in Collection on Digital System Design by the same author.

• History of Device Simulator.

In early 1970, numerical processor was coupled with device simulators in SUPREM and SEDAN at Stanford University. These were 1-D programs.

SEDAN could analyze devices with five metallurgical junctions. Here device analysis was carried out by solving Poisson Equation and transient current continuity equation. This gave the potential distribution and carrier concentration distribution in Silicon devices. In Table 7.1 we give the chronological development of Device Simulator.

Table 7.1. Chronological Development of Device Simulator.

7.6. History of Process Simulators.

Process Simulator models all the fabrication steps encountered in IC Chip fabrication such as: oxidation, implantation, diffusion, etching, deposition and lithography.

Early models depended on analytical equations. But with smaller dimensions, second order effects became significant. Hence numerical analysis became inevitable.

With shrinking dimensions, according to Moore’s law, 3-D analysis of devices has become important. Later versions of SUPREM have these capabilities.

7.7. Evolution of TCAD.

TCAD modeling based on computer simulation spans the interrelated disciplines of circuit design, device engineering, process development and integration into manufacturing. TCAD is routinely used for process and device development.

TCAD is used for rapid prototyping as well to study new device structures and discover newer terminal characteristics.

SUPREM for process simulation and PISCES for device simulation have been commercialized by Technology Modeling Associates(TMA) by the name TSUPREM4 and MEDICI respectively. Silvaco bought the license and offered the same by the name ATHENA and ATLAS. Integrated Systems Engineering(ISE) offered its own version of process and device simulator by the name DIOS and DESSIS. ISE has since merged with Synopsis.