9.1 Sspd_chapter 7_part 1_the art of microchip fabrication transforms  (Page 3/4)

Global entities, such as clock signals and supply lines, are significantly

affected by scaling.

􀂁New design issues emerge over time.

Power dissipation issue periodically re-emerges.

􀂁Trouble shooting an erroneous design requires circuit expertise.

􀂁 And : You need to know it for doing the class assignments and project.

Figure 7.5. Functional testing of the VLSI System.

Figure 7.5. Functional and Parametric Testing.

7.3. History of Chip Design

[“The History of Custom MOS Design”, Steve Golson,Trilobyte Systems,Email: sgolson@trilobyte.com

Web: (External Link) ]

1968 – This was the beginning Custom MOS design.

• Hand-drawn schematics

• Standard cells -- new library for each product line

~ 6 kinds of gates, ~ 4-5 speed ranges

• Gate sizing by hand using CT curves (load vs delay)

• Place&route by hand on rubylith mylar sheets

• TTL breadboard for verification

• Transistor-level timing analysis using SPICE-like programs

Designer thinks about:

Gates, transistors, breadboard, and maybe library

Early 1970s -- some improvements

+ Module-level design (multiple designers working on one chip)

+ Software simulation (cycle-based)

+ On-chip bus design (trade wires for time)

+ Pitch-matched layout (datapath, PLA, ROM, RAM)

+ MOS-specific circuit techniques (dynamic logic)

Designer thinks about:

Gates, netlist simulation, floorplan, transistors

Early 1980s -- LSI Logic et al.

Hand-drawn schematics

• Hand-typed netlist

+ Automatic place and route

• Netlist simulation

+ Gate-level timing analysis

Designer thinks about:

1. Gates, netlist simulation
2. Mid 1980s -- some improvements

Schematic capture

+ Automatic netlist generation

• Automatic place and route

• Netlist simulation

• Gate-level timing analysis

Designer thinks about:

1. Gates, netlist simulation
2. Early 1990s -- Verilog and synthesis

RTL Verilog

+ RTL simulation

+ Synthesized netlist

• Netlist simulation

• Automatic (?) place and route

• Gate-level timing analysis

Designer thinks about:

1. RTL code, RTL simulation, gates, netlist simulation
2. Late 1990s -- Behavioral synthesis

Behavioral Verilog, some generated by graphical HLDA tools

+ Behavioral Verilog and HLDA simulation

• RTL Verilog, some automatically generated by HLDA tool

• RTL simulation

• Synthesized netlist

• Netlist simulation

• Automatic (???) place and route

• Gate-level timing analysis

1. + FPGA breadboard

Late 1990s -- Behavioral synthesis

Designer thinks about:

Behavioral code, RTL code, gates, floorplan,

1. behavioral simulation, RTL simulation, netlist simulation, breadboard

2001 and beyond the infinite…

+ System design language (C++, Superlog, SystemC, etc.)

+ System design language simulation

+ System design language synthesis

• RTL Verilog

• RTL simulation

• Floorplan

• RTL synthesized netlist&placement (physical synthesis)

• Netlist simulation

1. • Gate-level timing analysis

2001 and beyond the infinite…

Designer thinks about:

System code, RTL code, gates, floorplan, placement,

1. system simulation, RTL simulation, netlist simulation, breadboard
2. Levels of abstraction today…

[Steve Golson -- Trilobyte Systems -- Levels of Abstraction: The History of Custom MOS Design]

Levels of abstraction today…