8.5 Sspd_chapter 6_part 4_the instability of mos in 60s and its  (Page 2/3)

Case 1. When gate voltage is (-) ve we get accumulation layer at the interface of Si/SiO ₂ .

The negative charge on the gate (Q _g ) is exactly balanced by the accumulation of holes (Q _a ) in the substrate just below the oxide layer. There is band bending in the Si-substrate due to the negative gate bias. This band bending results in valence band coming nearer to the Fermi-level as shown in Figure 6.33. This results in P-type semi-conductor becoming more P-type resulting in accumulation layer of holes just under the oxide layer. If at high frequency from (100kHz to 1MHz) the small signal capacitance is measured , the capacitance value is :

C _ox = (ε ₀ ε _oxide )A/(t _oxide )_______________________________________________(6.6)

The measured value is given in upper part of Figure 6.32.

Figure 6.33 Creation of Accumulation layer below the oxide layer in the Si-substrate under (-)ve gate bias in an ideal MOS diode where energy band is flat when gate bias is zero.

Case 2. When gate voltage is zero we get flat band condition since we have assumed ideal MOS diode.

Ideal MOS Diode has the following properties:

1. Energy Band is flat under no bias condition as shown in Figure 6.34;
2. Only charges are in the channel and in the gate and they are equal and opposite;
3. No carrier transport.

As seen in Figure 6.34, there is no band bending and if the small signal capacitance is measured at HF we get slightly less than C _ox as indicated in the middle diagram of Figure 6.32.

Case 3. When gate voltage is (+) ve biased then the holes in the substrate nearest the interface are pushed away from the interface and depletion layer ‘d’micron wide is formed. The positive gate charge is balanced by the exposed (-) ve ionic immobile charge in the depletion layer. This (-) ve ionic immobile charge is due to negatively charged Boron atoms which have created the holes and in the process, by acquiring electrons, have become negatively charged.

The positive gate charge Q _g = Q _d the depletion layer negative charge.

Now if small signal capacitance is measured at HF we measure the series combination of C _ox and C _D

where C _D = [ε ₀ ε _Si A/d] and d = depletion width___________________________(6.7)

The measured C = [C _ox × C _D /( C _ox + C _D )]________________________________(6.8)

The measured value of C is shown in the middle diagram of Figure 6.32

Figure 6.35 MOS Diode under positive gate bias.

Case 4. When Gate bias voltage exceeds threshold voltage.

The depletion layer will go on widening until threshold voltage is crossed. At the crossing of the Threshold Voltage , the layer of the substrate below the oxide layer is inverted as shown in Figure 6.36. P-type becomes N-type over a thin layer called inversion layer. A 2-D sheet of electron channel is formed just underneath the oxide later amounting to Q _i . Now the increase in gate bias voltage causes the electron density to become more copious. That is the channel becomes more conductive. But the depletion layer gets pinned at d _max. . In other words increase in gate charge Q _g is balanced by increase in Q _i in steady state condition or in slow variation condition.