8.29 Sspd_chapter 6_part 9_appendix device physics  (Page 8/8)

where k=dielectric constant or relative permittivity of the gate insulator

d=thickness of the gate insulator and A= cross-sectional area of the gate insulator.

Metal interconnects are preferred over low-k material so that propagation delay is minimized.

Low k will give higher velocity of propagation thereby minimizing the propagation delay.

MOS capacitance had to be reproducible, its behavior should be repeatable. To achieve this reproducibility and repeatability, Reactive Sputtering or Metal Organic CVD had to be abandoned in favour of Atomic Layer Deposition . This gave the necessary smoothness to the surface of the electrode as well as precise control over the thickness of the Gate Insulator. This ensured reproducibility and repeatability.

Several dielectrics were studied such as Al ₂ O ₂ , TiO ₂ , Ti ₂ O ₂ , Ti ₂ O ₅ , HfO ₂ , HfSiO ₄ , ZrO ₂ , ZrSiO ₂ , La ₂ O ₃ .

With scaling due to Fermi-Level pinning , higher threshold Voltage (V _Thres ) resulted. Also High-k material have high elasticity hence result in higher phonon scattering or lattice scattering resulting in lower channel mobility. By screening the phonon effect, the deterioration in channel conductivity could be prevented. This required increasing the electron density in Poly-Si gate. Hence we had to switch to Metal-High k combination. This prevented:

1. Fermi-Level pinning hence threshold voltage normalized;
2. This normalized channel conductivity which had drastically deteriorated due to dipole vibration effect;
3. Metal Gate Electrode provides better bonding between Metal-Dielectric. Hence stable operation.

In mid-2003, Intel’s Hillsbaro, Ore, Development Fab developed HK-MG CMOS. Intel’s 130nm technology was used. Using Hafnium-Based Oxide and Metal Gate electrode following characteristics were achieved:

1. Low Threshold = 1V;
2. Negligible leakage current through Oxide;
3. High 2-D channel mobility;

The standard fabrication method was “Gate First”. In this method:

Gate Dielectric+Gate Electrode were laid first;

Source and Drain implanted;

Silicon is annealed to repair the damages that occurred during ion-implantation. High Temperature became a problem for the new technology of HK-MG. So “Gate Last” technology was adopted which circumvented the annealing problem. This led to a paradigm shift in late 2004.

The new flow process was 45nm technology with High k + Metal Gate using Gate-Last strategy. Using this flow process in January 2006, 153Mb SRAM with 1 billion CMOS was built. Leakage gate current was reduced by a factor of 10. But there was sub-threshold leakage.

Scaling had reduced Threshold Voltage but reduced V _Th led to increased sub-threshold leakage which defeated the nanoWatt-logic objective. Each new generation of scaled down transistor would increase I _ON by about 30% but would lead to I _{sub-threshold} increase by 3-Fold. So at ULSI level, power efficiency and low leakage would be at premium rather than speed.

Table IV.The options at 45nm HK-MG CMOS Technology

The CMOS circuits are built between these two extremes.

PENRYN dual-core µP has 410mCMOS and PENRYN quad-core µP has 820 m CMOS. These are optimized for mobile applications, desk-top computers, 64-bit workstations and server applications.

Section III.8. Atomic layer Deposition

Dielectric Layers were deposited by Reactive Sputtering or by Metal Organic CVD. This left unevenness on the surface which caused charge trapping. There were charges stored at the interface too. These charges altered the behavior of MOS capacitance from discharge cycle to discharge cycle. So a deposition method had to be adopted which allowed dielectric deposition in controlled manner atom layer by layer.

Figure XIV. Methodology of Atomic Layer Deposition.

In Figure XIV the steps taken for Atomic Layer Deposition is illustrated. Gas1 reacts with bare Silicon surface to form a single atomic layer of insulator Si-Gas1. As soon as one layer is completed Gas1 stops reacting with Si because no bare Si is in contact with Gas1.

In step 2, Gas2 is chosen which is reactive with dielectric1 or Si-Gas1 insulator. Gas2 reacts with dielectric layer1 to form dielectric layer2 (Dielectric1-Gas2 insulator). As soon as dielectric layer2 covers the whole of dielectric1, reaction stops. Thus each reaction is terminated at the end of layer deposition. In this way we achieve layered gate insulator which is controllable down to the width of a single atom.

This produces much smoother dielectric hence the charge trapping is prevented . MOS produced is reproducible and stable in operation.