8.29 Sspd_chapter 6_part 9_appendix device physics  (Page 7/8)

Figure XI. In a HOMO JUNCTION of equal doping on two sides the total forward junction current is made up of 50% electrons being injected from N to P side and 50% holes being injected from P side to N side.

Figure XII. In a HETERO JUNCTION under forward bias the Built-in Barrier Potential are so unequal that Junction Current is wholly constituted of carriers injected from Wide Band Gap to Narrow Band Gap thereby automatically achieving 100% Injection Efficiency even without creating large doping differential on the two sides.

Thus we see that heterojunction are very naturally disposed towards giving 100% injection efficiency even with a very low base spreading resistance.

Section III.6. Fermi-level pinning and its prevention.

(academic.brooklyn.cuny.edu/physics/tung/Schottky/index.htm)

At Metal-ntype-Semiconductor interface we realize Schottky Barrier Diode. This exhibits a rectifying contact characteristic hence it has an in-built Schottky Barrier Height(SBH) as illustrated in Figure IV.1.

Figure XIII.. Asymptotic Energy Band Diagram of Metal-Semiconductor Interface and illustration of Schottky Barrier Potential Height.

It was found experimentally that SBH is insensitive to the Metal Work Function. This was defined as Fermi-Level pinning (FL pinning). It generally occurred at the mid-band gap of Semiconductor. This was always the case with polycrystalline MS interfaces and it was quite counterintuitive. In 1980s a few high quality, single crystal MS interfaces prepared and SBH measured. SBH was found to be sensitive to orientation/structure of MS interface. By spatially-resolved SBH measurement technique notably by Ballistic Electron Emission Microscopy(BEEM) it was found that SBH are inhomogeneous at polycrystalline MS interfaces and structure dependent at single crystal MS interfaces.

At the turn of the century when dipole associated with chemical bonding at MS interfaces was modeled using established methods borrowed from Molecular Physics it was shown that FL pinning was a natural consequence of interfacial bonding.

If minimization of total energy is applied

1. then it results in structure dependence of SBH at epitaxial interfaces and
2. SBH in homogeneity at polycrystalline interfaces.

By this theory FL pinning at polycrystalline MS interfaces and the pinning position at mid-band gap comes automatically.

This model is being further refined.

Section III.7. High-k solution for ULSI CMOS.[The high-k solution by Mark T. Bohr, Robert S. Chau, Tahir Ghani&Kaizad Mistry, IEEE Spectrum , October 2007, pp 23-29]

As the level of integration evolved, size of CMOS halved every 24 months. At this rate of scaling, by 1998 SiO ₂ gate insulation became 5 atomic layer thick with total thickness scaled to 13Aº each atomic layer being 2.6Aº. Current leakage and heating became a serious problem. Because of wave nature of electron and its quantum mechanical tunneling property, thin gate oxides allow the electrons accumulated on gate to leak to the channel. To overcome this problem we need physically thick gate oxides to prevent quantum mechanical tunneling but at the same time electrically thin so that channel is turned at low threshold. If dielectric constant is doubled then thickness can be doubled without any reduction in Turn-ON capability since C=kε ₀ A/d