8.12 Class test 1_25th_march_2011  (Page 2/2)

Figure 1.

Figure 2 is the photomicrograph of the layout.

Figure 3.This is manually drawn several times magnified layout of the monolithic circuit.

• Deep Brown is the isolation boundary.
• Navy Blue is the bonding pad.
• Sky Blue is the metallization.
• Golden yellow is the gold wire which is bonded to the peripheral bonding pad on one end and to the terminal of the IC package at the other end. This bonding is done either by Thermo-compression technique or by Ultra-sonic bonding technique.
• The die or the individual chip is mounted on ceramic substrate by means of solder glass. The ceramic substrate is attached to a suitable header by means of a high temperature eutectic solder or the die can be mounted in all ceramic flat package.
• The header is hermetically sealed by a suitable packaging material.

Design rules for Monolithic Circuit Layout.

1. Redraw the circuit to satisfy the required pin connections with minimum crossovers.
2. Determine the number of isolation islands from collector potential consideration and reduce the area as much as you can.
3. Place all the resistances in the same isolation island and this isolated island must be returned to the most positive voltage.
4. Resistances are realized by an elongated strip of P diffusion in N-epi layer. In order that resistances may be isolated from N-epi layer and hence from one another, N-epi layer corresponding to the island containing the resistances must be at the most positive potential namely Vcc.
5. The substrate must be at the most negative potential. In this case the GROUND potential.
6. Allow the isolation border to be equal to twice the epilayer thickness.
7. Use 1-mil width for diffused N+ emitter region.
8. Use ½ mil width for base contact and spacing.
9. Use ½ mil width for collector contact and spacing.
10. For resistances use widest possible design.
11. Keep metallization short and wide.

Solution of the problem:

1. Number of islands: Every distinct collector voltage will have one isolated island assigned to it. Here we have three transistors in one gate but at the same collector voltage therefore the two gates wil have two islands containing the two sets of three transistors.
2. This dual gate will have a third island which will be at the highest Positive Voltage Vcc and will contain the two sets of four resistances. Pin number 10 is connected to Vcc and is connected to the N-epilayer island containing all the resistances
3. The P ^- substrate will be held at the most negative voltage which in this case is Ground. Pin number 5 is the ground terminal and is connected to a bonding pad connected to the isolation boundary(deep brown colour) as shown.
4. The N-epilayer containing the transistors has one elongated N ⁺ diffusion to which Aluminum contact pad is made. This is the collector Contact Pad. This collector Contact Pad is connected to the Output Pad as well as to one end of the resistance R _C .
5. Similarly emitter contact pads are connected together and connected to ground.
6. The base Contact Pads are connected to R _B ’s which in turn are connected to the three input pads.
7. Fabrication Steps are:

1. Oxidation of the substrate of resistivity 10 Ω-cm.
2. Using Mask 1 , buried layer diffusion of Arsenic is done with sheet resistivity of 1 Ω/sq.
3. Oxide layer is completely etched away and epitaxial layer of N type Silicon is grown of resistivity 0.1Ω-cm.
4. Reoxidize and using Mask 2, isolation diffusion P-type is done to create isolated N-epi islands. Each island will contain BJTs or Diodes with collectors at one voltage.
5. Reoxidize and open windows by Mask 3 for Boron base diffusion and for Resistance diffusion (3R _B s and R _C ). All the resistances are located on the island which has its N-epi layer at V _CC .
6. Reoxidize and open windows by Mask 4 for Phosphorous emitter diffusion and for collector contact diffusion. Three separate emitters have to be defined and one elongated collector contact is defined.
7. Reoxidize and open apertures by Mask 5 for contact pads to 3 emitters, 3 bases and one elongated collector per gate. The contact pads are made to the two ends of the four resistances also per gate.
8. Final metallization is done covering the whole wafer and using Mask 6, the interconnection pattern is etched out as shown in Figure 3.
9. Golden yellow in Figgure 3 is the gold wire which is bonded to the peripheral bonding pad on one end and to the terminal of the IC package at the other end. This bonding is done either by Thermo-compression technique or by Ultra-sonic bonding technique.
10. The die or the individual chip is mounted on ceramic substrate by means of solder glass. The ceramic substrate is attached to a suitable header by means of a high temperature eutectic solder or the die can be mounted in all ceramic flat package.
11. The header is hermetically sealed by a suitable packaging material.