8.10 Sspd_chapter 6_part 6_mos ic's fabrication technology_to be  (Page 3/3)

6.6.3.5. Self-aligned Source and Drain fabrication.

Using mask 7 light doping implant of Phosphorous is done in NMOS area situated in P-tub as shown in Figure 6.64. Typically a dose of 5×10 ¹³ to 5×10 ¹⁴ per cm ² at 50keV is used.

Using mask 8 light doping implant of Boron is done in PMOS area situated in N-tub as shown in Figure 6.65. Typically a dose of 5×10 ¹³ to 5×10 ¹⁴ per cm ² at 50keV is used.

Once the light dose implant is completed, fixed KPR is completely removed from the surface of the wafer by stripper or oxygen plasma.

Note that in Figure 6.64 and in Figure 6.65, LDD implant lies under the edge of the gate. This has been achieved by tilted angle implant.

6.6.3.5.1 Sidewall Spacers along the edge of the PoySi gate.

Now we do LPCVD of a conformal spacer dielectric layer (SiO2 or Si3N4) on the wafer surface. The thickness of this layer will decide the width of the sidewall spacer which is chosen around 100nm to optimize the device characterisics.

At 400°C, SiH ₄ + O ₂ → SiO ₂ +2H ₂ ;

Or at 900°C, SiH ₂ Cl ₂ + 2N ₂ O → SiO ₂ + 2N ₂ +2HCl;

Conformal spacer dielectric layer deposition is obtained as shown in Figure 6.66. Note that the thickness of SiO ₂ is much thicker along the edges of the polysilicon as compared to that on the flat regions of the wafer surface. This thickening is caused due to conformal deposition on the vertical edge of the PolySi gate contact.

Now we use fluorine-based plasma to carry out highly anisotropic etching of SiO ₂ over the entire wafer area(etches vertically but not horizontally).

Deposited conformal layer of SiO ₂ is removed everywhere except at the vertical edges of PolySi gate contacts. Thus sidewall spacers are realized as shown in Figure 6.67. Note that SiO ₂ has been removed from Source and Drain region also as a part of the Sidewall Spacer formation process.

6.6.3.5.2. Final Source/Drain formation.

In the process of Sidewall Spacer formation, the oxide layer has been completely removed from Source and Drain regions also. So another 10nm SiO ₂ is thermally grown over the whole wafer area. This provides a 10nm ‘screen oxide’ in the source and drain regions as well as on top of the PolySi gate regions.

The ‘screen oxide’ is needed for the following reasons:

1. Oxide being amorphous it randomizes the implanted ions trajectory thereby preventing Chanelling Effect. The Silicon lattice is crystalline and if the ion velocity vector is aligned with the crystal structure of Silicon, ions can go down the “channels” between lattice centers for long distances without encountering Silicon atoms. If this happens, the range of implanted ions will be much larger than expected. This is undesirable hence ‘screen oxide’ is needed.
2. ‘screen oxide’ helps minimize the incorporation of trace impurities into the Silicon from the implanter system.

After ‘screen oxide’ has formed we use Mask 9, to selectively implant P-tub with N+ source and N+drain. The N+ implant is Arsenic because in modern devices we need shallow junctions in small geometry devices. An implant of high dose of 2×10 ¹⁵ to 4×10 ¹⁵ per cm ² at 75keV is used. This allows the implanted ions to cross ‘screen oxide’ but still be masked by fixed KPR. This completes the step of formation of (E)NMOS as shown in Figure 6.68.

Now Mask 10 is used to implant P+ Source and Drain of (E)PMOS in N-tub. For this using Mask 10 N-tub regions are kept exposed through appropriate windows in KPR layer. After developing the KPR layer, the existing KPR is hardened and is fixed in the oven so that it can shield the implanted ions from entering the shielded areas. The implant is high dose of Boron at less than 75keV. The dose itself is 1×10 ¹⁵ to 3×10 ¹⁵ per cm ² . Since Boron is lighter therefore it requires less energy to reach the same range.

In both these cases high dose implants have been used to minimize the parasitic resistances associated with the drain and sources. The final structure after the use of Mask 9 and 10 and after the final high temperature drive-in is as shown in Figure 6.69.

6.6.4. Why do we have LDD and sidewall spacers along the edges of PolySi Gate Contacts?

In VLSI era as we move to deep-sub-micron and ultra-deep-sub-micron devices we are forced to adopt small geometry and shallow junction devices. At these levels of miniaturization many new effects have shown up and which have to be taken care of. In Figure 6.70 we give the magnified view of Figure 6.69.

Because of the scaling trends and its concomitant effects we have been forced to introduce Lightly Doped Drain(LDD) or Lightly Doped Source and Sidewall Spacer along the edges of PolySi(N+) Gate Contact.

As device dimensions have been scaled the operating voltage has not been proportionately scaled as a result the average electric field has increased by one order of magnitude. This creates “hot electron” effects. The hot electron experiences “scatter limited velocity”. Here the drift velocity is not proportional to the electric field hence electron drift velocity in-effect saturates.

Plus “hot electron” cause carrier injection into gate oxide by overcoming the Si/Silicon Oxide interface potential barrier of 3.2eV. These carriers trapped in oxide will cause instability.

By grading the doping of Drain and Source from N+ to N- Lightly Doped Drain(LDD) , we allow the drain voltage to drop over larger distances leading to reduction in the peak of the electric field caused from Drain To Source. Even modest reduction in the peak electric field leads to significant improvement in the reliability of the device.

At deep-sub-micron level, short channel effect show up in a big way. Theoretically in Pentode Region, the Drain Current should be a function of Gate Voltage only but due to channel length modulation Drain Current is a function of Drain Voltage also as shown in Equation 6.23.

Where λ is channel length parameter it varies from 0.001 to 0.1 per volt.

As device geometry is scaled, this channel length parameter increases. By use of shallow junction this parameter can be minimized. LDD provides this shallow junction. To achieve LDD we use light dose implants along with sidewall spacer.

This sums up the reasons why LDD and sidewall spacer is used along the edge of PolySi Gate contact.