4.6 2.1.2. solid state era  (Page 5/11)

2.1.2.3. Microcomputer Era- the beginning of Personal Computer Revolution.

In 1971, Intel marketed micro-processor μP4004 – a 4-bit central processing unit.It combined the function of 12 subsystems on one single Si-die. It was 1cm×1cm die with 2300(E)PMOS employing 10μm-process Technology which cost $299 and in India it could be obtained for Rs 7,500. It had a clock rate of 184kHz. Assuming 2 machine cycles per instruction it could carry out 92,000 Instructions Per Second. In 2010 Intel is accommodating 560Mega CMOS employing 32nm-process technology and second generation high K-metal Gate Si- technology.

In 1974, IBM’s Robert Dennnard, inventor of single transistor DRAM(Dynamic RAM) showed that when MOSFET geometries, voltages and dopings were scaled down, gate transit time also scaled down and performance thus improved by the same factor. [“Design of Ion-Implanted MOSFET with very small Physical Dimensions”, IEEE Journal of Solid State Circuits, Vol.SC-9,No.5, 256-268,October 1974]. Taken together, density improvement as predicted by Moore’s Law and the performance improvement by Dennard signaled a coming explosion of growth in chip processing power. This precisely happened and this is what has been fueling Computer-Communication Revolution till date.

In 1976, Xerox PARC(Palo Alto Research Center) and CALTECH,Pasadena, launched a joint collaborative programme on Electrooniuc Design Automation(EDA) to deal with the complex task of future chip designing where integration level will exceed 100,000 components. By 1979, Lee Conway and Carver Mead invented the Scalable Design Rules and Structured Design Methodology from top-to-bottom. Their work was incorporated in ‘The introduction to VLSI Systems’ published by Addison-Wesley. Soon after MPC79 programme was launched coordinated by ARPANET. [“Reminiscences of the VLSI Revolution- How a series of failures triggered a paradigm shift in digital design”, Lee Conway, IEEE Solid State Circuits Magazine, Fall 2012, Vol.4, No.3, pp.8-32].

Under MPC79, 12 Universwities participated with LSI Design Courses being offered at Graduate level in Fall Semester. In all 82 design projects from 124 designers spread across 12 die-typesa on two wafer sets were completed. Turnaround time from design cut-off to distribution of packaged chips was only 29 days. At second VLSI Conference in January 1980 the detailed results of MPC79 were presented.

DARPA (Defense Advanced Research Project Agency) seeing the potential of VLSI Design Methods allocated $50 million to VLSI Research. PARC MPC system Technology and Methods of Operation were transferred to University of South Carolina-ISI (a major DARPA software contractor). ISI announced MOSIS service. It is a Multi-Project Wafer Integrated Circuits Service Provider- one of the oldest foundries. Universities and small companies had access to state of art digital technology. On the way it may be mentioned that Advanced Computation System at IBM had pioneered the super-scalar architecturte of μPs and all high performance μP are based on this architecture.