4.1 - interrupts  (Page 3/3)

When the end of the ISR is reached the MSP executes a precise set of steps to pick up the execution of the program where it left off before the interrupt occurred. This process takes 5 cycles.

• The status register and all previous settings pops from the stack. Any alterations to the status register made during the interrupt are wiped away.
• The program counter pops from the stack and execution continues from where it left off.

Interrupt enable registers

Using interrupts successfully is not as simple as just writing an interrupt service routine and waiting for the event to occur. Because you do not necessairly want to activate every interrupt in the processor at once, the MSP allows you to mask out certain interrupts. When the triggering event first occurs, the processor checks whether the interrupt is enabled before jumping to the interrupt service routine. For most interrupts, the MSP checks the general interrupt enable bit in the status register and the particular interrupt’s enable in the interrupt enable registers. If both of these have been configured to allow the interrupt, then the processor enters the interrupt service routine if the event in question has occurred.

By default most interrupts are turned off upon reset. To use most peripheral modules you will need to set the enable bits in the interrupt enable registers and turn on the general interrupt enable. Enabling sometimes causes the interrupt flag to be set, so you should consult the User’s guide on the best order to handle the enabling. Usually to properly configure the interrupt, you will also need to have set up the peripheral module in question before enabling the interrupt.

There are three categories of interrupts for the purpose of masking in the ez430. Reset interrupts, non-maskable non-reset interrupts, and maskable interrupts.

Maskable interrupts are the lowest priority interrupts and can be turned off individually with the various interrupt enable registers or turned off as a group by setting the general interrupt enable bit (GIE) in the status register (SR).

Non-maskable interrupts are not subject to the general interrupt enable (GIE). However each non-maskable interrupt source can be controlled by a bit to specifically turn it on or off. These are the flash access violation interrupt enable (ADDVIE), external NMI interrupt enable (NMIIE), and the oscillator fault interrupt enable (OFIE). All three of these bits are located in the interrupt enable register 1 (IE1).

Reset interrupts have the highest priority and will always reset the execution of the device. The external reset can be configured to trigger either the reset interrupt or an NMI interrupt.

The interrupt enable registers (IE1 and IE2) are used to individually enable the interrupts. Refer to the ez430's User’s Guide and Data sheet for the specifics of each peripheral. The example code on Ti's website are also very helpful when learning how to use interrupts. The procedures followed are drawn from the instructions and notes in the documentation. Often the relevant information may not be in one chapter or section of the guides. This is part of the reason working examples are essential to developing a working knowledge of the processor.

More detailed information on the operation of interrupts can be found in the MSP User’s Guide. Unfortunately the material is generally found in the chapter for each subsystem. The general interrupt information is found in chapter 2.