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The MSP430 contains built-in features for both parallel and serial data communication. This chapter describes the operation of these peripherals, and discusses the protocols, data formats and specific techniques for each type of data communication.
The communication modules available for the MSP430 family of microcontrollers are USART (Universal Synchronous/Asynchronous Receiver/Transmitter), USCI (Universal Serial Communication Interface) and USI (Universal Serial Interface). These provide asynchronous data transmission between the MSP430 and other peripheral devices when configured in UART mode. They also support data transmission synchronized to a clock signal through a serial I/O port in Serial Peripheral Interface (SPI) and Inter Integrated Circuit (I2C) modes.
This laboratory explores the USCI and USI communication interfaces in I 2 C mode. It uses the two MSP430 devices included on the Experimenter’s board: MSP430FG4618 as the master and the MSP430F2013 as the slave. The master receives a single byte from the slave as soon as a button connected to P1.0 is pressed.
This laboratory uses the USCI module of the MSP430FG4618 device and the USI module included in the MSP430F2013. Both units operate in I2C mode.
The interrupts on the slave unit are generated exclusively by the USI module. They are:
- START condition in the I2C bus;
- Data reception and transmission.
The interrupts on the master unit are provided by the USCI module. They are:
- Data reception;
- Interrupt on Port1.
The resources used are:
- USCI module;
- USI module;
- Interrupts;
- I/O ports.
The software architecture for this laboratory is shown in Figure 1.
The master task is composed of two interrupt service routines ( Lab3_Comm_1.c ):
- S1 switch service routine used to receive a new frame from the slave;
- USCI module interrupt service routine that reads the data sent by the slave.
Software architecture
For the operational capability of the slave unit based on the USI module, it is necessary to implement a state machine as shown in Figure 2. It is important to note that the states “RX Address” and “RX (N)ACK" are transient states that ensure the USI module is prepared for the next activity.
Slave state machine.
The connection via I 2 C bus will operate in the following mode:
- Address slave with 7-bit address;
- Master mode;
- Single master;
- USCI clock source is SMCLK;
The following control registers are configured based on these characteristics:
UCB0CTL0 = 0x0F;
//UCB0CTL0 = UCA10 | UCSLA10 | UCMM | Unused | UCMST | UCMODEx | UCSYNC//UCA10 (Own address) = 0b ->Own address (7-bit)
//UCSLA10 (Slave address) = 0b ->7-bit slave address
//UCMM (Multi-master) = 0b ->Single master
//Unused//UCMST (Master mode) = 1b ->Master mode
//UCMODEx (USCI mode) = 11b ->I2C Mode
//UCSYNC (Synchronous mode enable) = 1b ->SynchronousUCB0CTL1 = 0x81;//UCB0CTL1 = UCSSELx | Unused | UCTR | UCTXNACK | UCTXSTP | UCTXSTT | UCSWRST//UCSSELx (USCI clock source select) = 10b ->SMCLK
//Unused//UCTR (Transmitter/Receiver) = 0b ->Receiver
//UCTXNACK (Transmit a NACK) = 0b ->ACK normally
//UCTXSTP (Transmit STOP condition) = 0b ->No STOP
//UCTXSTT (Transmit START condition) = 0b ->No START
//UCSWRST (Software reset) = 1b ->Enabled
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