1.4 Central processing unit (msp430x cpu)

Central processing unit (msp430x cpu)

Main features of the msp430x cpu architecture

The MSP430X CPU extends the addressing capabilities of the MSP430 family beyond 64 kB to 1 MB. To achieve this, there are some changes to the addressing modes and two new types of instructions. One type of new instructions allows access to the entire address space, and the other is designed for address calculations.

The MSP430X CPU address bus is 20 bits, but the data bus is still 16 bits. The CPU supports 8-bit, 16-bit and 20-bit memory accesses. Despite these changes, the MSP430X CPU remains compatible with the MSP430 CPU, having a similar number of registers. A block diagram of the MSP430X CPU is shown in the figure below:

Msp430x cpu block diagram.

Although the MSP430X CPU structure is similar to that of the MSP430 CPU, there are some differences that will now be discussed.

With the exception of the status register SR, all MSP430X registers are 20 bits. The CPU can now process 20-bit or 16-bit data.

Msp430x cpu registers

R0 (pc) - program counter

Has the same function as the MSP430 CPU, although now it has 20 bits.

R1 (sp) - stack pointer

Has the same function as the MSP430 CPU, although now it has 20 bits.

R2 (sr) - status register

Has the same function as the MSP430 CPU, but still only has 16 bits.

Description of the sr bits.

R2 (cg1) and r3 (cg2) - constant generators

The registers R2 and R3 can be used to generate six different constants commonly used in programming, without the need to add an extra 16-bit word of code to the instruction. The constants below are chosen based on the bit (As) of the instruction that selects the addressing mode.

Values of constant generators.

Whenever the operand is one of these six constants, the registers are selected automatically. Therefore, when used in constant mode, registers R2 and R3 cannot be addressed explicitly by acting as source registers.

R4-r15 – general-purpose registers

These registers have the same function as the MSP430 CPU, although they now have 20 bits. They can store 8-bit, 16-bit or 20-bit data. Any byte written to one of these registers clears bits 19:8. Any word written to one of these registers clears bits 19:16. The exception to this rule is the instruction SXT, which extends the sign value to fill the 20-bit register.

The following figures illustrate how the operations are conducted for the exchange of information between memory and registers, for the following formats: byte (8 bits), word (16 bits) and address (20 bits).

The following figure illustrates the handling of a byte (8 bits) using the suffix .B.

Example: register-byte/byte-register operation.

The following figure illustrates the handling of a word (16-bit) using the suffix .W.

Example: register-word/word-register operation.

Example: register-word/word-register operation.

The following figure illustrates the manipulation of an address (20 bits) using the suffix .A.

Example: register - address-word operation.

Example: address-word - register operation.

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