1.17 50 years journey of ic technology_appendix ix_history of sige  (Page 2/2)

Where

τ _E = RC delay time constant at EB junction;

τ _C = RC delay time constant at CB junction;

τ _B = Transit time delay through Base Width;

τ _CSCL = Transit time delay through reverse biased CB junction;

v _S = scatter limited velocity of electrons while falling down the potential hill at CB junction;

To achieve this objective , we must simultaneously reduce the two transit times, cross-sectional area of capacitances and series resistances. Introduction of C in SiGe base has helped reduce R _sh of Base even after thinning as required in vertical scaling.

Reduction in time delay requires that quiescent I _C is increased which means that Kirk Effect must be pushed to high Current Density. This is achieved by increasing Collector Dopant Concentration for which we do Selectively Implanted Collector(SIC).

SIC allows higher values of I _C , decreases R _C and reduces W _CSCL . But increase in SIC, means more lateral and vertical diffusion in subsequent heat cycles which leads to higher C _CB . So vertical and lateral scaling should be carefully controlled to maximize f T and f max .

Table IX.2. Milestones of Development of SiGe-strained Si FETs.

SiGe Technology has become the driving force behind the explosion in low cost, light weight, personal communication devices like digital wireless handsets and other entertainment and information technologies such as Digital Set-Top Boxes, Digital Broadcast Satellites, Automobile Collision Avoidance and Personal Digital Assistants. SiGe extends the life of wireless phone batteries and allows more durable communication devices. Products combining the capabilities of Cellular Phone, Global Positioning and Internet access in one package are designed using SiGe.

These multi-function, low cost mobile client devices capable of communication over voice and data networks represent a key element of the future of computing.

SiGe HBT in CMOS for high end PC failed but SiGe HBT succeeded in RF Communication Circuits because of low power consumption.

SiGe Technology is finding extensive applications in:

Wired Communication;

Wireless Communication Circuits;

In Disk Storage;

High speed BW instrumentation;

Discrete SiGe HBT in Amplifiers and Wireless Devices;

IC SiGe HBT in GSM handsets, in CDMA hand sets, in Base stations, in Wireless LAN chipsets and in high speed 10-40Gb/s Synchronous Optical Networks(SONETS) receivers.

Ge grading in Base helps higher transit frequency f _T and increase in short circuit current gain β _F . By suitable trading of β _F with r _x ( base spreading resistance), BW can further be improved. By increased Base Doping, r _x reduces. This reduction adversely effects β _F but gives considerable improvement in transit frequency and in Noise Figure of the device. For same I _C (collector current) , SiGe HBT has a higher short circuit current gain, lower RF noise and lower flicker noise or 1/f noise as compared to an identical Si BJT. In SiGe , higher raw speed and lower power consumption can be traded depending upon the application.

Table IX.3 Comparison of CMOS with conventional Si-BJT and SiGe HBT ( after Harame)

Real strength of SiGe lies in Analog, RF and Digital Applications in existing CMOS Fabrication Foundaries. This makes possible implementation of new Architecture such as direct conversions and software defined radio.

SiGe BiCMOS Technology.

This technology demands that Low Temperature Epitaxy(LTE) SiGe process be combined with high temperature CMOS processing.

CMOS performance must be retained ( same as the parent CMOS process) after the addition of LTE SiGe in order to use existing digital ASIC Libraries and Design Methodologies.

Similarly CMOS processing must not significantly alter the doping profile ( and hence performance) of SiGe HBT.

In this integration the two primary issues are thermal budget and trade off between process modularity and process sharing.

IBM first generation (5HP) 0.5µm SiGe BiCMOS used a “base equal gate” scheme. A common layer stack is used for both HBT base and FET poly-Si Gates.

Problem arises when CMOS advances to 0.24µm Technology(6HP). At this point CMOS thermal cycle increased significantly because of the need for Source/Drain dopant activation for NMOS and gate side wall oxidation. So “ base after gate” strategy is adopted. HBT is built after the formation of gate, gate spacer, LDD implants and NMOS anneals. This simplified BiCMOS integration of SiGe HBT with newer generation of CMOS.