| << Chapter < Page | Chapter >> Page > |
Appendix IX.
History and Physics of SiGe HBT.
[Overview: Fabrication of SiGe HBT Bi-CMOS Technolgy- Cressler]
Table IX.1. History of SiGe HBT.
| Device | Year of first intoduction | Reference |
| First epitaxial BJT | 1960 | Theurer,Kleimeck, Loar&Christemer, “Epitaxial Diffused Transistor”, Proceedings of IRE 48, 1642-1643,1960. |
| First SiGe HBT | 1987 | Iyer, Patton, Delage, Tiwari&Stork, “ Silicon-Germanium Base heterojunction bipolar transistors by MBE,” Technical Diget of IEEE International Election Device Meeting, San Francisco, 1987, 874-876. |
| First ideal SiGe HBT by CVD | 1989 | King, Hoyt, Gronet, Gibbons, Scott&Turner, “Si/Si (1-x) Ge x heterojunction Transistor produced by limited reaction processing,” IEEE ED Letters, 10, 52-54,1989. |
| First SiGe HBT by UHV/CVD | 1989 | Patton, Harame, Stork, Meyerson, Scilla and Ganin, “ Graded-SiGe-Base, poly-emitter heterojunction bipolar transistors,” IEEE ED Letters 10, 534-536, 1989. |
| Fiirst High performance SiGe HBT | 1990 | |
| First self-aligned SiGe HBT | 1990 | |
| First SiGe HBT ECL ring oscillator | 1990 | |
| First pnp SiGe HBT | 1990 | |
| First operation of SiGe HBTs at cryogenic temperature | 1990 | |
| First SiGe HBT BiCMOS Technology | 1992 | |
| LSI SiGe HBT IC(12 bit DAC-1.2GS/sec) | 1993 | |
| First SiGe HBT with peak f T =100GHz | 1993 | |
| First SiGe HBT in 200mm Wafer Technology | 1994 | |
| First SiGe HBT Technology optimized at 77K | 1994 | |
| First Radiation Tolerance investigation of SiGe HBT | 1995 | |
| First Report of Low Frequency Noise in SiGe HBT | 1995 | |
| First SiGe:C HBT | 1996 | |
| First High power SiGe HBT | 1996 | |
| First sub-10psec SiGe HBT in ECL circuit | 1997 | |
| First High Performance SiGe:C HBT Technology | 1999 | |
| First SiGe HBT with peak f T above 200GHz | 2001 | |
| First SiG HBT with peak f T above 300GHz | 2002 | |
| First complementary symmetry amplifier using HBT | 2003 | |
| First C:SiGe Technology with npn&pnp f T above 100GHz | 2003 | |
| First vertical SiGe HBT on thin film SOI(CMOS compatible) | 2003 | |
| First SiGe HBT with both f T and f max above 300GHz | 2004 | |
Steps in SiGe HBT fabrication.
Step 1. Low Sheet Resistance Buried layer is fabricated: High dose Arsenic implant followed by a long thermal cycle in oxidizing ambient. This drives Arsenic deep in the wafer and anneals the defects caused by ion-implantation. A thin epi-layer is deposited at high temperature. The buried layer has a sheet resistance of R sh = 10Ω/▄ .
Alternatively
Sub-collector may be just implanted in the wafer. This wafer is more compatible for CMOS processing. Burt since no following anneal step, hence to minimize the defects, dose and depth of implant is considerably less and R sh = 100Ω/▄ .
Combination of deep trench isolation and buried sub-collector leads to reduced Collector Capacitance and reduced Collector Resistance therefore maximum f T and f max can be realized.
In advanced HBT structure scaling involves both vertical and lateral scaling.
Vertical Scaling:
Vertical scaling consists of thinning all the three layers of HBT(base, collector and emitter). The base width is scaled by shrinking the base width and increasing Ge gradient across the base which includes increasing the peak Ge%. If all doped regions are thinned then transit time may decrease but RC time constant increases because R increases. To get an overall improvement in f T overall time delay τ EC must be brought down.
Notification Switch
Would you like to follow the 'Solid state physics and devices-the harbinger of third wave of civilization' conversation and receive update notifications?
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|