Descriptions & Requirements
and Requirements
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect.
Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.
We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
Join us to transform the future through continuous technological innovation.
You Are:
You are a highly skilled Analog Design Engineer with a passion for designing, developing, and evaluating physical IP such as SERDES, DDR, and Memory.
You thrive in a collaborative environment and are adept at tackling complex design challenges.
Your expertise in PHY Power Delivery and Power Integrity, combined with your knowledge of system modeling, system margin, and jitter, makes you a valuable asset to any team.
You are proactive, detail-oriented, and possess excellent problem-solving skills.
With minimal oversight, you take initiative on new or special assignments and communicate effectively with both internal and external stakeholders.
Your extensive expertise and innovative mindset contribute significantly to the success of the organization.
What You'll Be Doing:
Review UCIe and other D2D standards to develop novel transceiver architectures and sub-block specifications.
Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area and performance targets.
Designing, developing, and evaluating analog circuits of the fast-growing high-speed Die to Die interconnect IP portfolio Conducting system modeling, system margin analysis, and jitter analysis to ensure robust and high-performance designs Work across geography, project, department teams to streamline design and verification strategies ensure overall design quality, efficiency and performance.
Oversee PHY level physical layout to minimize the effect of parasitics, device stress, and process variation.
Present & review simulation data from internal project teams.
Present results externally at industry panels or at customer reviews.
Document design features and test plans.
Consult on the overall electrical characterization of the D2D IP product.
Analyze customer silicon data for design enhancements.
Propose solutions for post-silicon design updates.
Collaborating with cross-functional cross-geo teams to define design specifications and requirements, and enable prompt what-if system level analysis from customer Mentor and train highly matrixed global design team members to build best in class Die to Die Interconnect solutions across technology nodes Conducting design reviews and providing technical guidance to junior engineers in highly matrixed global design organization Staying updated with the latest industry trends and technological advancements to incorporate innovative solutions into your designs.
The Impact You Will Have:
Enhancing the performance and reliability of Synopsys' physical IP products.
Driving innovation in analog design to meet the evolving demands of the semiconductor industry.
Contributing to the development of cutting-edge technologies that shape the future of computing and connectivity.
Collaborating with diverse teams to deliver high-quality solutions that exceed customer expectations.
Strengthening Synopsys' reputation as a leader in chip design and IP integration.
Fostering a culture of continuous improvement and technical excellence within the organization.
What You'll Need:
PhD with 10+ years, or MSc with 12+ years of practical analog IC design experience; degree in Electrical Engineering or Computer Engineering or other relevant field of study.
Experience with FinFET technologies Extensive design experience with sub-circuits relevant to Memory/SerDes/D2D:
Receive equalizers such as CTLE, DFE, FFE DAC Based transmitters and ADC based receivers, DSP equalization High speed clocking circuits such as PLL, VCO, ILO, DLL and phase interpolator Duty Cycle Correction, Clock Phase Correction Circuits Digitally Assisted Analog Calibration Loops In depth familiarity with transistor level circuit design - sound CMOS design fundamentals, experience with CMOS tape-outs Knowledge of high speed SerDes/Memory/D2D IO, circuit and fabrication issues that directly impact customer use-cases.
Aware of ESD issues (i.e.
circuit techniques, layout).
Familiarity with custom digital design (i.e.
high-speed logic paths, Serializer, De-serializer).
Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc.) Knowledge of design for reliability (i.e.
EM, IR, aging, self-heating, etc.) and layout effects (i.e.
matching, reliability, proximity effects, etc.).
Experience with tools for schematic entry, physical layout, and design verification.
Knowledge of SPICE simulators and simulation methods.
Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.
Excellent communication, presentation, and documentation skills
Who You Are:
Innovative thinker with a passion for solving complex design challenges.
Excellent communicator with the ability to convey technical concepts to diverse audiences.
Collaborative team player who thrives in a dynamic, fast-paced environment.
Detail-oriented and highly organized, with a commitment to delivering high-quality results.
Proactive problem solver who takes initiative and demonstrates strong leadership skills.
The Team You'll Be A Part Of:
You will be part of a talented and dedicated team of engineers focused on the design and development of high-performance analog IP.
Our team collaborates closely with other engineering disciplines to deliver innovative solutions that meet the rigorous demands of the semiconductor industry.
We value creativity, technical excellence, and a collaborative spirit, and we are committed to supporting your growth and success within the organization.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
Our total rewards include both monetary and non-monetary offerings.
Your recruiter will provide more details about the salary range and benefits during the hiring process.
Inclusion and Diversity are important to us.
Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses.
Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package.
The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.
Your recruiter can share more specific details on the total rewards package upon request.
The base salary range for this role is across the U.S.
US - OR - OR - Roseburg
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December 19, 2024
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US - OR - OR - Salem
December 19, 2024
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December 19, 2024
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US - OR - OR - Bend
December 19, 2024
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December 19, 2024
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December 19, 2024
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December 19, 2024
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December 19, 2024
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December 19, 2024
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December 19, 2024
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US - OR - OR - Portland
December 19, 2024
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US - OR - OR - Salem
December 19, 2024
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December 19, 2024
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December 19, 2024
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December 19, 2024
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