HBM Memory Subsystem Architect - Technical Leadership Member - TPG

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our Opportunity Summary:


For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies. We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

Our HBM Design Architecture group is looking for an experienced Memory Subsystem Architect to work with internal and external partners to investigate, define, and develop innovative new memory subsystem architectures building on our Industry leading HBM product solutions. The AI/ML transformation underway is demanding breakthrough memory and computing solutions, and we believe our HBM product roadmap is foundational in enabling these new innovative solutions. The HBM Design Architecture group collaborates closely with Industry partners to investigate and develop products aligned with customer needs and technology trends extending over 3-5 year timeframe.

In HBM DEG (High Bandwidth Memory - DRAM Engineering Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and testing (validation) of HBM is the most challenging due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting.

Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies! Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity.

(Disclaimer):
While you may not exhibit all of the characteristics/skills listed below today, we are highly interested in a teammate who is motivated to grow in technical breadth and depth. Suppose you are open to learning while being a valued member of a team of best-in-class engineers. In that case, we are determined to help build upon your existing foundation, while rapidly growing your individual and collaborative skills in this exciting and outstanding opportunity.
• This position will be a hybrid role located in either Allen, TX, Atlanta, GA, or, Folsom, CA
• The seniority level offered will be based on a combination of experience and education. What's Encouraged Daily:

• Help develop innovative new memory subsystem frameworks for HBM solutions targeting AI/ML applications
• Includes PHY, memory controllers, NOC, microcontrollers, MBIST, interfaces, adapters, RAS, buffers, etc for various memory types (DDR, LPDDR, HBM)
• Responsible for defining Memory and RAS requirements and architecture
• Work with internal and external partners for developing novel architectures and defining detailed requirements for all vital IP
• Drive the engagement with IP vendors and the selection of various interface and functional IP
• Analyze various benchmarks, workloads, and simulation results to identify areas for memory subsystem innovation
• Perform performance and performance/watt modeling, estimate gate count, power, area
• Create architectural specifications and external-facing documents. Work with partners to generate specifications considering various hardware and protocol standards
• Collaborate with the RTL and validation teams to ensure successful and on-time design implementation of all subsystem features
• Prepare material for and participate in design reviews related to HBM products and memory subsystems
• Collaborate with internal and external partners on architectural decisions, development flows and tools
• Participate in performance simulation and benchmarking of features and memory and computing architectures to drive better architectural decision-making
• Drive the memory subsystem microarchitecture definition and specification process
• Debug performance and functional issues with high-level models, RTL simulation, hard and soft IP, etc

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 10 years of experience in memory subsystem architecture and design.
• Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM).
• Experience with PHY design and understanding of signal integrity issues.
• Proficiency in Network-on-Chip (NoC) architecture and design.
• Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, HIF, etc
• Strong analytical and problem-solving skills
• Excellent written and verbal communication skills

• PhD in a relevant field
• Familiarity with EDA tools for design and verification
• Practical experience with multi-core systems, coherent interconnects & Industry IO protocols like PCIe/CXL, confidential computing, virtualization & security
• Knowledge of serial link protocols (UCIe etc. ) is desired