6.1 Laboratory signal acquisition: lab2 - sar adc12 conversion

Laboratory signal acquisition: lab2 - sar adc12 conversion

Introduction

This laboratory gives examples of the uses of the ADC types available in the hardware development kits. A different laboratory is developed for each kit, taking into account that both the ADC10 and the SD16_A laboratories implement a temperature data logger. The ADC12 laboratory also uses operational amplifiers to perform the analogue signal conditioning.

Overview

This laboratory (Lab2_ADC.c) examines the ADC12 and OA modules using the MSP-EXP430FG4618 Development Tool (MSP430FG4618 device). The test voltage is generated by the DAC12 channel 0, available in DAC12_ODAT register. The analogue signal is conditioned by the OA module (amplitude change), configured as non-inverting operational amplifier. Afterwards, this signal is applied to the ADC12 input to be converted. Compare the DAC12_ODAT and the ADC12MEM0 values.

Resources

The DAC12 module uses the same internal reference voltage as the ADC12 module (V _REF+ = 2.5 V).

The OA module is configured as Non-inverting PGA with unity gain. The Non-inverting input is the DAC0 internal while the output is connected to internal/external A1 of the ADC12. The ADC12 sample-and-hold time is configured to be 64 ADC12CLK cycles. It performs a single-channel, single-conversion using ADC12OSC/1 as the clock source.

The resources used by the application (following the signal modification steps) are:

- DAC12;

- OA;

- ADC12;

- Timer_A;

- Interrupts.

Software application organization

The laboratory is organized following its working flow chart:

- Peripheral initialization phase, finishing with the MSP430 in LPM3;

- ISR phase, consisting of a Timer_A overflow service routine that triggers a new ADC12 conversion and it is responsible by the end of conversion.

The application starts by stopping the Watchdog Timer.

The system clock is configured by the FLL+ at 4.199304 MHz (128 x 32768Hz).

The DAC12 module is configured to present a null voltage (0 V) at the output. It uses the ADC12 internal 2.5 V reference voltage. The DAC12’s output is configured with 12-bit resolution, in straight binary. DAC12 uses the full-scale output with a Medium speed/current.

The OA module is configured as non-inverting PGA, the input signal (DAC0 internal) being in the rail-to-rail range. The output of the OA is connected to internal/external A1.

The ADC12 is configured to perform a single-channel (channel A1), single-conversion. The configuration includes the activation of the same internal reference voltage as the DAC12. The ADC12 clock source is ADC12OSC, with the sample-and-hold time selected as 64 ADC12CLK cycles.

The Timer_A is configured to use the ACLK as the clock source. It will count in continuous mode (TACCR0 counts up to 0FFFFh) and generate an interrupt to update the ADC12MEM. When the interrupt is serviced, the MSP430 enters into LPM3.