Control systems lab introduction, hardware, software, and safety  (Page 3/3)

Pxi-1042 chassis

The National Instruments PXI-1031 chassis provides a foundation to which a variety of PXI expansion modules can be added. This makes it a highly customizable measurement andtesting platform.

Pxi-8186 real-time embedded controller

The National Instruments PXI-8186 is a Pentium4-based, real-time embedded controller. In addition tohaving the ability to act as a Windows PC, the PXI-8186 can also run an NI developed, real-time operating system which allows it towork as a deployment platform for LabVIEW Real-Time applications.

Pxi-7831r reconfigurable multifunction i/o

The National Instruments PXI-7831R Reconfigurable Multifunction I/O is a module that can input and output both analog and digital signals. It is equipped with an FPGA(field processor gate array) which is configurable with the LabVIEW FPGA Module.

Safety procedures

The following procedures are to help prevent damage to the lab equipment and also to ensure your safety. Be sureto read and understand all of the information in this section before performing any experiments. Should you ever have anyquestions regarding the operation of the lab hardware, do not hesitate to ask the instructor.

General safety precautions

• Always check to make sure that all of the system components (brass weights, disks, spring, etc) are securely fastened beforepowering on the ECP amplifier box and implementing your VI.
• Whenever you are reconfiguring the plant setup, always be sure to check that your VI is not running and that the amplifierbox is turned off.
• When implementing an untested control algorithm, check for stability by using a long slender object (such as a ruler orunsharpened pencil) to apply gentle force to the mass/disk nearest to the drive motor.
• Do not disturb the system while it is executing a commanded trajectory.
• In the event of an emergency, shut off power to the system by pressing the red button on the amplifier box.

Hardware limits on the model 210

Located near each mass carriage are two stop bumpers that prevent the carriage from exceeding their maximumallowable displacement. On each stop bumper is an electrical switch which sends out a signal when it is engaged. When the LabVIEW FPGAcode receives this signal, it immediately outputs zero command voltage to the drive motor. This voltage remains zero until theerror is cleared via the control loop VI's front panel. In addition to the limit switches, the FPGAcode has been written to prevent overspeed / overvoltage of the drive motor. When the code detects overspeeding / overvolting ofthe motor, it will again output zero command voltage and remain there until the error has been cleared.

Hardware limits on the model 205

The FPGA code for the model 205 plant has been written to detect when the relative position between the firstand second disks exceeds 3000 counts. This is to prevent damage to the torsional rod if a large torque is applied to the base disk.When this limit is exceeded, zero command voltage is output to the drive motor until the error is cleared. Just as with the model 210 plant, the model 205 also has drive motor over-speed/overvoltage protection incorporated into the FPGA code.