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Disadvantage of TLB scheme: if two pages use the same entry of the memory, only one of them can be remembered at once. If processis referencing both pages at same time, TLB does not work very well.
Example: TLB with 64 (100 octal) slots. Suppose the following virtual pages are referenced (octal): 621, 2145, 621, 2145, ... 321,2145, 321, 621.
TLBs are a lot like hash tables except simpler (must be to be implemented in hardware). Some hash functions are better thanothers.
Another approach: let any given virtual page useeither of two slots in the TLB. Make memory wider, use two comparators to check both slots at once.
Must be careful to flush TLB during each context swap. Why?
In practice, TLB's have been extremely successful with 95% or great hit rates for relatively small sizes.
As address spaces have grown to 64 bits, the side of traditional page tables becomes a problem. Even with two-level (or even three orfour!) page tables, the tables themselves can become too large.
A solution (used on the IBM Power4 and others) to this problem has two parts:
With an inverted page table, most address translations are handled by the TLB. When there is a miss in the TLB, theoperating is notified (via an interrupt) and TLB miss-handler is invoked.
The operating system can sometimes be thought of as an extension of the abstractions provided by the hardware. However, when thetable format is defined by the hardware (such as for a page table entry), you cannot change that format. So, what do you do if you wanted to store additionalinformation, such as last reference time or sharing pointer, in each entry?
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