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The system clock is configured to operate with a frequency of ~ 1048 kHz from the DCO. This frequency will be the working base frequency of the USCI module. The connection operates at a clock frequency of ~ 95.3 kHz:
// DATA RATE
// data rate ->fSCL = SMCLK/11 = 95.3kHz
UCB0BR0 = 0x0B; // fSCL = SMCLK/11 = 95.3kHzUCB0BR1 = 0x00;
In order to set the external interfaces at the USCI module, it is necessary to configure the I/O ports. Select the USCI peripheral in I 2 C mode matching the connections provided at the Experimenter’s board:
P3SEL |=0x06; // Assign I2C pins to USCI_B0
The connection via I 2 C bus will operate in the following mode:
- Slave mode;
- USI counter interrupt enable (RX and TX);
- START condition interrupt-enable;
- USIIFG is not cleared automatically.
The following control registers are configured based on these characteristics:
USICTL0 = 0XC1;//USICTL0 = USIPE7 | USIPE6 | USIPE5 | USILSB | USIMST | USIGE | USIOE | USISWRST
//USIPE7 (USI SDI/SDA port enable) = 1b ->USI enabled
//USIPE6 (USI SDO/SCL port enable) = 1b ->USI enabled
//USIPE5 (USI SCLK port enable) = 0b ->SCLK disable
//USILSB (LSB first) = 0b ->MSB first
//USIMST (Master) = 0b ->Slave mode
//USIGE (Output latch control) = 0b ->Output latch
// enable depends on shift clock//USIOE (Serial data output enable) = 0b ->Output enable
//USISWRST (USI software reset) = 1b ->Software resetUSICTL1 = 0x70;//USICTL1 = USICKPH | USII2C | USISTTIE | USIIE | USIAL | USISTP | USISTTIFG | USIIFG
//USICKPH (Clock phase select) = 0b ->Data is changed
// on the first SCLK edge and captured on the following edge.//USII2C (I2C mode enable) = 1b ->I2C mode enabled
//USISTTIE = 1b ->Interrupt on START condition enabled
//USIIE = 1b ->USI counter interrupt enable
//USIAL (Arbitration lost) = 0b ->Not used
//USISTP (STOP condition received) = 0b ->Not used
//USISTTIFG (START condition int. flag) = 0b ->Not used
//USIIFG (USI counter int. flag) = 0b ->No int. pending
The slave unit interrupt service routine is not complete. The portion related to the “I2C_TX” state needs to be completed:
- Configure the USI module as output;
- Insert the information to transmit using the transmission register;
- Configure the bit counter.
// USI Bit Counter Register
USICNT |= 0x20;//USICNT = USISCLREL | USI16B | USIIFGCC | USICNTx//USISCLREL (SCL release) = 0b ->SCL line is held low
// if USIIFG is set//USI16B (16-bit shift register enable) = 0b ->8-bit
// shift register mode//USIIFGCC (USI int. flag clear control) = 1b ->USIIFG
// is not cleared automatically//USICNTx (USI bit count) = 00000b ->(not relevant)// I2C state machine:
USICTL0 |= USIOE; // SDA = outputUSISRL = SlaveData; // Send data byte
USICNT |= 0x08; // Bit counter = 8, TX data
Once the USCI module is configured in accordance with the previous steps, initiate the experiment with the files ( Lab3_Comm_1.c ) (master – MSP430FG4618) and ( Lab3_Comm_2.c ) (slave – MSP430F2013), compiling them and running them on the Experimenter’s board.
For this laboratory, the following jumper settings are required:
- PWR1/2, BATT, LCL1/2, JP2;
- SPI: H1- 1&2, 3&4.
The slave data is sent and increments from 0x00 with each transmitted byte, which is verified by the Master. The LED is off for address or data Acknowledge and the LED turns on for address or data Not Acknowledge. LED3 blinks at each data request. It is turned on with a START condition and it is turned off by the data transmit acknowledge by the slave (Note: the I 2 C bus is not released by the master since the successive START conditions are interpreted as “repeated START”).
Verify the value received setting a breakpoint in the line of code “
RxBuffer = UCB0RXBUF; ” of the USCI interrupt.
This example and many others are available on the MSP430 Teaching ROM.
Request this ROM, and our other Teaching Materials here (External Link)
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