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After you have the filter coefficients, take the two’s complement by using twocomplement.m . You need them in that format in order to use them in the A/D-D/A conversion. Make sure you divide the coefficients by two before taking the two’s complement. To include them in your file, use the save_coeff.m function to create an assembly file.
Download the following files to give you a good starting point: [Insert code files here]Read through the files and give a brief description of each one.
The serial peripheral interface (SPI) is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1-16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals, the DAC in our case, or another controller.
To implement the FIR filter, the DSP must be set up to communicate with the DAC on the daughtercard. Set up the SPI registers on the F2812 DSP by assigning the following values to the corresponding registers:
| Register Name | Register Value (HEX) |
|---|---|
| SPICCR.bit.SPISWRESET | 0 |
| SPICCR.all | 0x005F |
| SPICTL.all | 0x001F |
| SPISTS.all | 0x0000 |
| SPIBRR.all | 0x0002 |
| SPIFFTX.all | 0xC028 |
| SPIFFRX.all | 0x0028 |
| SPIFFCT.all | 0x00 |
| SPIPRI.all | 0x0010 |
| SPICCR.bit.SPISWRESET | 1 |
| SPIFFTX.bit.TXFIFO | 1 |
| SPIFFRX.bit.RXFIFORESET | 1 |
Which register is set to:
The F2812 DSP has a 12-bit ADC core with built-in dual sample-and-hold (S/H). Its options include:
A block diagram of the ADC module from TI documents:
Set the following ADC registers as follows:
| Register Name | Register Value (HEX) |
|---|---|
| AdcRegs.ADCMAXCONV.all | 0x0001 |
| AdcRegs.ADCCHSELSEQ1.bit.CONV00 | 0x3 |
| AdcRegs.ADCCHSELSEQ1.bit.CONV01 | 0x2 |
| AdcRegs.ADCTRL2.bit.EVA_SOC_SEQ1 | 1 |
| AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 | 1 |
The event manager peripheral in the DSP includes general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. You will use event manager A (EVA) to trigger the SOC sequence in the ADC.
EVA functional diagram from TI documents:
Set the following EVA registers as follows and describe what each one will do:
| Register Name | Register Value (HEX) |
|---|---|
| EvaRegs.T1CMPR | 0x00fa |
| EvaRegs.T1PR | 0x1f4 |
| EvaRegs.GPTCONA.bit.T1TOADC | 1 |
| EvaRegs.T1CON.all | 0x1043 |
Interrupts, as described by Dr. Choi in one of his lab manuals in ELEC 434, provide a mechanism for handling any infrequent or exception event. The interrupt causes a CPU to make a temporary transfer of control from its current location to another location that services the event. Variety of sources, internal and external to the CPU, can generate interrupts. The use of interrupts greatly increases the performance of the CPU by allowing the I/O devices direct and rapid access to the CPU and by freeing the CPU from the task of continually testing the status of its I/O devices. The I/O devices assert interrupts to request the CPU to start a new I/O operation, to signal the completion of an I/O operation, and to signal the occurrence of hardware and software errors.
The F2812 DSP supports one nonmaskable interrupt (NMI) and 16 maskable prioritized interrupt requests (INT1-INT14, RTOSINT, and DLOGINT) at the CPU level.
Program the interrupts for the ADC and the SPI along with the functions for:
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