0.14 Mix’n’match receiver design  (Page 3/9)

The channel may be near ideal (i.e., a unit gain multisymbol delay) or it may have significant intersymbol interference.In either case, the impulse response of the channel is unknown at the receiver, though an upper bound on itsdelay spread may be available. There are also disturbances that may occur during thetransmission. These may be wideband noise with flat power spectral density or they may be narrowband interferers, or both.They are unknown at the receiver.

The achieved intermediate frequency is required to be within $0.01$ percent of its assigned value. The carrier phase $\theta \left(t\right)$ is unknown to the receiver and may vary over time, albeit slowly.This means that the phase of the intermediate frequency signal presented to the receiver sampler may also vary.

The bandpass filter before the downconverter in the front-end of the receiver in [link] partially attenuates adjacent 204 kHz wide FDM user bands. The automatic gain control is presumed locked and fixedover each transmission. The free-running sampler frequency of 850 kHz is well abovetwice the 102 kHz baseband bandwidth of the user of interest. This is necessary for the baseband analog signal interpolatorused in the timer in the DSP portion of the receiver in [link] . However, the sampler frequency is not abovetwice the highest frequency of the IF signal. This means that the sampled received signal has replicated thespectrum at the output of the front-end analog downconverter lowpass filter to frequencies between zero and IF.

A design methodology for the ${\mathcal{M}}^6$ Receiver

Before describing the specific design requirements that must be metby a successful ${\mathcal{M}}^6$ receiver, this section makes some generic remarks about a systematic approach toreceiver design. There are four generic stages:

1. Choose the order in which the basic operations of the receiver occur.
2. Select components and methods that can perform the basic operations in an ideal setting.
3. Select adaptive elements that allow the receiver to continue functioning when there are impairments.
4. Verify that the performance requirements are met.

While it may seem as though each stage requires that choices made in the preceding stages be fixed, in reality, difficulties encountered at one stage in the design processmay require a return to (and different choices to be made in) earlier stages.As will soon become clear, the ${\mathcal{M}}^6$ problem specification has basically (pre)resolved thedesign issues of the first two stages.

Stage one: ordering the pieces

The first stage is to select the basic components and the order in which they occur.The design layout first established in [link] (and reappearing in the schematic of the DSP portion of the receiver in [link] ) suggests one feasible structure. As the signal enters the receiver it is downconverted(with carrier recovery), matched filtered, interpolated (with timing recovery), equalized (adaptively),quantized, and decoded (with frame synchronization). This classical ordering, while popular, is not theonly (nor necessarily the best) way to recover the message from the noisy, ISI-distorted, FDM–PAM–IF received signal.However, it offers a useful foundation for assessing the relative benefits and costs of alternativereceiver configurations. Also, we know for sure that the ${\mathcal{M}}^6$ receiver can be built this way. Other configurations may work, but we have not testedthem. If this sounds like a challenge, rest assured it is. Research continues worldwide, making compilation of acomplete handbook of receiver designs and algorithms a Sisyphean task. The creation of “new” algorithms with minor variations thatexploit a particular application-specific circumstance is a popular pastime of communication engineers.Perhaps you too will come up with a unique approach!